EBD21RD4ABNA-10 データシートの表示（PDF） - Elpida Memory, Inc
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EBD21RD4ABNA-10 Datasheet PDF : 19 Pages
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EBD21RD4ABNA
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 200 µs and then, execute power on sequence and auto refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to VSS
VT
–1.0 to +3.6
V
Supply voltage relative to VSS
VDD, VDDQ
–1.0 to +3.6
V
Short circuit output current
IOUT
50
mA
Power dissipation
PT
18
W
Operating ambient temperature
TA
0 to +70
°C
1
Storage temperature
Tstg
–55 to +125
°C
Note: 1. DDR SDRAM device specification
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit Notes
Supply voltage
VDD,VDDQ
2.3
2.5
2.7
V
1
VSS
0
0
0
V
Input reference voltage
VREF
0.49 × VDDQ
0.50 × VDDQ 0.51 × VDDQ
V
Termination voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
Input high voltage
VIH (DC)
VREF + 0.15
—
VDDQ + 0.3
V
2
Input low voltage
VIL (DC)
–0.3
—
VREF – 0.15
V
3
Input voltage level,
CK and /CK inputs
VIN (DC)
–0.3
—
VDDQ + 0.3
V
4
Input differential cross point
voltage, CK and /CK inputs
VIX (DC)
0.5 × VDDQ − 0.2V 0.5 × VDDQ 0.5 × VDDQ + 0.2V V
Input differential voltage,
CK and /CK inputs
VID (DC)
0.36
—
VDDQ + 0.6
V
5, 6
Notes: 1.VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable dc execution of each differential input.
5. VID (dc) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Preliminary Data Sheet E0273E20 (Ver. 2.0)
10
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