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ADSP-2195MKCA-160 データシートの表示(PDF) - Analog Devices

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ADSP-2195MKCA-160
ADI
Analog Devices ADI
ADSP-2195MKCA-160 Datasheet PDF : 68 Pages
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ADSP-2195
For current information contact Analog Devices at 800/262-5643
Table 7. Pin Descriptions (Continued)
September 2001
Pin
Type Function
MS3–0
O/T External Port Memory Space Selects
BR
I
External Port Bus Request
BG
O
External Port Bus Grant
BGH
O
External Port Bus Grant Hang
HAD15–0
I/O/T Host Port Multiplexed Address and Data Bus
HA16
I
Host Port MSB of Address Bus
HACK_P
I
Host Port ACK Polarity
HRD
I
Host Port Read Strobe
HWR
I
Host Port Write Strobe
HACK
O
Host Port Access Ready Acknowledge
HALE
I
Host Port Address Latch Strobe or Address Cycle Control
HCMS
I
Host Port Internal Memory–Internal I/O Memory–Boot Memory Select
HCIOMS
I
Host Port Internal I/O Memory Select
CLKIN
I
Clock Input/Oscillator input
XTAL
O
Oscillator output
BMODE1–0 I
OPMODE
I
Boot Mode 1–0. The BMODE1 and BMODE0 pins have 85 kinternal pull-up resistors.
Operating Mode. The OPMODE pin has a 85 kinternal pull-up resistor.
CLKOUT
O
Clock Output
BYPASS
I
Phase-Lock-Loop (PLL) Bypass mode. The BYPASS pin has a 85 kinternal pull-up
resistor.
RCLK1–0
I/O/T SPORT1–0 Receive Clock
RCLK2/SCK1 I/O/T SPORT2 Receive Clock/SPI1 Serial Clock
RFS1–0
I/O/T SPORT1–0 Receive Frame Sync
RFS2/MOSI1 I/O/T SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input data
TCLK1–0
I/O/T SPORT1–0 Transmit Clock
TCLK2/SCK0 I/O/T SPORT2 Transmit Clock/SPI0 Serial Clock
TFS1–0
I/O/T SPORT1–0 Transmit Frame Sync
TFS2/MOSI0 I/O/T SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input data
DR1–0
I/T SPORT1–0 Serial Data Receive
DR2/MISO1 I/O/T SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output data
DT1–0
O/T SPORT1–0 Serial Data Transmit
20
This information applies to a product under development. Its characteristics and specifications are subject to change with-
REV. PrA
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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