ADSP-2195MKCA-160 データシートの表示（PDF） - Analog Devices
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ADSP-2195MKCA-160 Datasheet PDF : 68 Pages
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September 2001 For current information contact Analog Devices at 800/262-5643
ADSP-2195
Table 7. Pin Descriptions (Continued)
Pin
DT2/MISO0
TMR2–0
RXD
TXD
RESET
TCK
TMS
TDI
TDO
TRST
EMU
VDDINT
VDDEXT
GND
NC
Type Function
I/O/T SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output data
I/O/T Timer output or capture
I
UART Serial Receive Data
O
UART Serial Transmit Data
I
Processor Reset. Resets the ADSP-2195 to a known state and begins execution at the program
memory location specified by the hardware reset vector address. The RESET input must be
asserted (low) at power-up. The RESET pin has a 85 kΩ internal pull-up resistor.
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK pin has a 85 kΩ
internal pull-up resistor.
I
Test Mode Select (JTAG). Used to control the test state machine. The TMS pin has a 85 kΩ
internal pull-up resistor.
I
Test Data Input (JTAG). Provides serial data for the boundary scan logic. The TDI pin has
a 85 kΩ internal pull-up resistor.
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
I
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the ADSP-2195. The TRST pin has a 65 kΩ
internal pull-down resistor.
O
Emulation Status (JTAG). Must be connected to the ADSP-2195 emulator target board
connector only.
P
Core Power Supply. Nominally 2.5 V dc and supplies the DSP’s core processor. (four pins).
P
I/O Power Supply; Nominally 3.3 V dc. (nine pins).
G
Power Supply Return. (twelve pins).
Do Not Connect. Reserved pins that must be left open and unconnected.
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
21
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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