ADSP-2195MKCA-160 データシートの表示（PDF） - Analog Devices

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ADSP-2195MKCA-160

DSP Microcomputer

Analog Devices 

35(/,0,1$5< 7(&+1,&$/ '$7$

September 2001 For current information contact Analog Devices at 800/262-5643

ADSP-2195

As indicated in Table 6, the OPMODE pin has a dual role,

acting as a boot mode select during reset and determining

SPORT or SPI operation at runtime. If the OPMODE pin

at reset is the opposite of what is needed in an application

during runtime, the application needs to set the OPMODE

bit appropriately during runtime prior to using the corre-

sponding peripheral.

Booting Modes

The ADSP-2195 has seven mechanisms (listed in Table 6)

for automatically loading internal program memory

after reset.

Table 6. Select Boot Mode (OPMODE, BMODE1, and

BMODE0)

Function

0 0 0 Execute from external memory 16 bits

(No Boot)

0 0 1 Boot from EPROM

0 1 0 Boot from Host

0 1 1 Reserved

1 0 0 Execute from external memory 8 bits

(No Boot)

1 0 1 Boot from UART

1 1 0 Boot from SPI, up to 4K bits

1 1 1 Boot from SPI, >4K bits up to

512K bits

The OPMODE, BMODE1, and BMODE0 pins, sampled

during hardware reset, and three bits in the Reset Configu-

ration Register implement these modes:

• Execute from memory external 16 bits—The memory

boot routine located in boot ROM memory space

executes a boot-stream-formatted program located at

address 0x10000 of boot memory space, packing 16-bit

external data into 24-bit internal data. The External Port

Interface is configured for the default clock multiplier

(128) and read waitstates (7).

• Boot from EPROM—The EPROM boot routine located

in boot ROM memory space executes a boot-stream-for-

matted program located at address 0x00000 of boot

memory space, packing 8- or 16-bit external data into

24-bit internal data. The External Port Interface is con-

figured for the default clock multiplier (32) and read

waitstates (7).

• Boot from Host—The (8- or 16-bit) Host downloads a

boot-stream-formatted program to internal or external

memory. The Host’s boot routine is located in internal

ROM memory space and uses the top 16 locations of

Page 0 program memory and the top 272 locations of

Page 0 data memory.

The internal boot ROM sets semaphore A (an IO register

within the host port) and then polls until the semaphore

is reset. Once detected, the internal boot ROM will remap

the interrupt vector table to Page 0 internal memory and

jump to address 0x0000 internal. From the point of view

of the host interface, an external host has full control of

the DSP's memory map. The Host has the freedom to

directly write internal memory, external memory, and

internal I/O memory space. The DSP core execution is

held off until the Host clears the semaphore register. This

strategy allows the maximum flexibility for the Host to

boot in the program and data code, by leaving it up to

the programmer.

• Execute from memory external 8 bits (No Boot)—

execution starts from Page 1 of external memory space,

packing either 8- or 16-bit external data into 24-bit

internal data. The External Port Interface is configured

for the default clock multiplier (128) and read waitstates

(7).

• Boot from UART—The Host downloads

boot-stream-formatted program using an autobaud

handshake sequence. The Host agent selects a baud rate

within the UART’s clocking capabilities. After a hardware

reset, the DSP’s UART transmits 0xFF values (eight bits

data, one start bit, one stop bit, no parity bit) until

detecting the start of the first memory block. The UART

boot routine is located in internal ROM memory space

and uses the top 16 locations of Page 0 program memory

and the top 272 locations of Page 0 data memory.

• Boot from SPI, up to 4K bits—The SPI0 port uses the

SPI0SEL1 (reconfigured PF2) output pin to select a

single serial EPROM device, submits a read command at

address 0x00, and begins clocking consecutive data into

internal or external memory. Use only SPI-compatible

EPROMs of ≤ 4K bit (12-bit address range). The SPI0

boot routine located in internal ROM memory space

executes a boot-stream-formatted program, using the top

16 locations of Page 0 program memory and the top 272

locations of Page 0 data memory. The SPI boot configu-

ration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1,

8-bit data, and MSB first.

• Boot from SPI, from >4K bits to 512K bits—The SPI0

port uses the SPI0SEL1 (re-configured PF2) output pin

to select a single serial EPROM device, submits a read

command at address 0x00, and begins clocking consecu-

tive data into internal or external memory. Use only

SPI-compatible EPROMs of ≥ 4K bit (16-bit address

range). The SPI0 boot routine located in internal ROM

memory space executes a boot-stream-formatted

program, using the top 16 locations of Page 0 program

memory and the top 272 locations of Page 0 data memory.

REV. PrA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

15

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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