ADSP-2195MKCA-160 データシートの表示（PDF） - Analog Devices

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ADSP-2195MKCA-160

DSP Microcomputer

Analog Devices 

35(/,0,1$5< 7(&+1,&$/ '$7$

ADSP-2195

For current information contact Analog Devices at 800/262-5643

September 2001

Bus Request and Bus Grant

The ADSP-2195 can relinquish control of the data and

address buses to an external device. When the external

device requires access to the bus, it asserts the bus request

(BR) signal. The (BR) signal is arbitrated with core and

peripheral requests. External Bus requests have the lowest

priority. If no other internal request is pending, the external

bus request will be granted. Due to synchronizer and arbi-

tration delays, bus grants will be provided with a minimum

of three peripheral clock delays. The ADSP-2195 will

respond to the bus grant by:

• Three-stating the data and address buses and the MS3–0,

BMS, IOMS, RD, and WR output drivers.

• Asserting the bus grant (BG) signal.

The ADSP-2195 will halt program execution if the bus is

granted to an external device and an instruction fetch or

data read/write request is made to external general-purpose

or peripheral memory spaces. If an instruction requires two

external memory read accesses, the bus will not be granted

between the two accesses. If an instruction requires an

external memory read and an external memory write access,

the bus may be granted between the two accesses. The

external memory interface can be configured so that the

core will have exclusive use of the interface. DMA and Bus

Requests will be granted. When the external device releases

BR, the DSP releases BG and continues program execution

from the point at which it stopped.

The bus request feature operates at all times, even while the

DSP is booting and RESET is active.

The ADSP-2195 asserts the BGH pin when it is ready to

start another external port access, but is held off because

the bus was previously granted. This mechanism can be

extended to define more complex arbitration protocols for

implementing more elaborate multimaster systems.

Instruction Set Description

The ADSP-2195 assembly language instruction set has an

algebraic syntax that was designed for ease of coding and

readability. The assembly language, which takes full

advantage of the processor’s unique architecture, offers the

following benefits:

• ADSP-219x assembly language syntax is a superset of and

source-code-compatible (except for two data registers

and DAG base address registers) with ADSP-218x family

syntax. It may be necessary to restructure ADSP-218x

programs to accommodate the ADSP-2195’s unified

memory space and to conform to its interrupt vector map.

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical

arithmetic add instruction, such as AR = AX0 + AY0,

resembles a simple equation.

• Every instruction, but two, assembles into a single, 24-bit

word that can execute in a single instruction cycle. The

exceptions are two dual word instructions. One writes 16-

or 24-bit immediate data to memory, and the other is an

absolute jump/call with the 24-bit address specified in the

instruction.

• Multifunction instructions allow parallel execution of an

arithmetic, MAC, or shift instruction with up to two

fetches or one write to processor memory space during a

single instruction cycle.

• Program flow instructions support a wider variety of con-

ditional and unconditional jumps/calls and a larger set of

conditions on which to base execution of conditional

instructions.

Development Tools

The ADSP-2195 is supported with a complete set of

software and hardware development tools, including Analog

Devices’ emulators and VisualDSP++® development envi-

ronment. The same emulator hardware that supports other

ADSP-219x DSPs, also fully emulates the ADSP-2195.

The VisualDSP++ project management environment lets

programmers develop and debug an application. This envi-

ronment includes an easy-to-use assembler that is based on

an algebraic syntax; an archiver (librarian/library builder),

a linker, a loader, a cycle-accurate instruction-level simula-

tor, a C/C++ compiler, and a C/C++ run-time library that

includes DSP and mathematical functions. Two key points

for these tools are:

• Compiled ADSP-219x C/C++ code efficiency—the

compiler has been developed for efficient translation of

C/C++ code to ADSP-219x assembly. The DSP has

architectural features that improve the efficiency of

compiled C/C++ code.

• ADSP-218x family code compatibility—The assembler

has legacy features to ease the conversion of existing

ADSP-218x applications to the ADSP-219x.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved

source and object information)

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

• Trace instruction execution

• Perform linear or statistical profiling of program

execution

• Fill, dump, and graphically plot the contents of memory

• Source level debugging

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and

manage DSP software development. Its dialog boxes and

property pages let programmers configure and manage all

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This information applies to a product under development. Its characteristics and specifications are subject to change with-

REV. PrA

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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