ADSP-21161NKCA-100(RevA) データシートの表示（PDF） - Analog Devices

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ADSP-21161NKCA-100
(Rev.:RevA)

DSP Microcomputer

Analog Devices 

ADSP-21161N

TIMING SPECIFICATIONS

The ADSP-21161N’s internal clock switches at higher frequen-

cies than the system input clock (CLKIN). To generate the

internal clock, the DSP uses an internal phase-locked loop

(PLL). This PLL-based clocking minimizes the skew between

the system clock (CLKIN) signal and the DSP’s internal clock

(the clock source for the external port logic and I/O pads).

The ADSP-21161N’s internal clock (a multiple of CLKIN)

provides the clock signal for timing internal memory, processor

core, link ports, serial ports, and external port (as required for

read/write strobes in asynchronous access mode). During reset,

program the ratio between the DSP’s internal clock frequency

and external (CLKIN) clock frequency with the CLK_CFG1–0

and CLKDBL pins. Even though the internal clock is the clock

source for the external port, it behaves as described in the Clock

Rate Ratio chart in Table 3 on Page 17. To determine switching

frequencies for the serial and link ports, divide down the internal

clock, using the programmable divider control of each port

(DIVx for the serial ports and LxCLKD for the link ports).

Note the following definitions of various clock periods that are a

function of CLKIN and the appropriate ratio control.

Figure 10 enables Core-to-CLKIN ratios of 2:1, 3:1, 4:1, 6:1,

and 8:1 with external oscillator or crystal. It also shows support

for CLKOUT-to-CLKIN ratios of 1:1 and 2:1.

Table 5. CLKOUT and CCLK Clock Generation Operation

Timing Requirements

Description1

CLKIN

CLKOUT

PLLICLK

CCLK

tCK

tCCLK

tLCLK

tSCLK

tSDK

tSPICLK

Input Clock

External Port System Clock

PLL Input Clock

Core Clock

CLKIN Clock Period

(Processor) Core Clock Period

Link Port Clock Period

Serial Port Clock Period

SDRAM Clock Period

SPI Clock Period

1 where:

LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD)

SR = serial port-to-core clock ratio (wide range, determined by CLKDIV)

SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register)

LCLK = Link Port Clock

SCLK = Serial Port Clock

SDK = SDRAM Clock

SPICLK = SPI Clock

Calculation

1/tCK

1/tCKOP

1/tPLLIN

1/tCCLK

1/CLKIN

1/CCLK

(tCCLK) × LR

(tCCLK) × SR

(tCCLK) × SDCKR

(tCCLK) × SPIR

SYNCHRONOUS EP

MULTIPROCESSING

SBSRAM

ASYNCHRONOUS EP

HOST

SRAM

HARDWARE

INTERRUPT

I/O FLAG

TIMER

CORE

I/O PROCESSOR

LINK PORTS

؋1, ؋1/2, ؋1/3, ؋1/4

CLKIN

(CRYSTAL OSCILLATOR

4.2–50MHz)

XTAL

(QUARTZ CRYSTAL

25MHz MAX)

CLOCK DOUBLER

؋1, ؋2

RATIOS

؋2, ؋3, ؋4

PLL

CLKDBL

CLKOUT CLK_CFG1–0

SDRAM

؋1, ؋1/2

SERIAL PORTS

؋1/2 MAX

SPI

؋1/8 MAX

Figure 10. Core Clock and System Clock Relationship to CLKIN

–20–

REV. A

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