ADSP-21161NKCA-100(RevA) データシートの表示（PDF） - Analog Devices
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ADSP-21161NKCA-100 Datasheet PDF : 60 Pages
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ADSP-21161N
Table 2. Pin Function Descriptions (continued)
Pin
WR
BRST
ACK
SBTS
CAS
RAS
SDWE
DQM
SDCLK0
SDCLK1
SDCKE
SDA10
IRQ2–0
FLAG11–0
TIMEXP
HBR
Type
I/O/T
I/O/T
I/O/S
I/S
I/O/T
I/O/T
I/O/T
O/T
I/O/S/T
O/S/T
I/O/T
O/T
I/A
I/O/A
O
I/A
Function
Memory Write Low Strobe. WR is asserted when ADSP-21161N writes a word to external
memory or IOP registers of other ADSP-21161Ns. External devices must assert WR for
writing to ADSP-21161N IOP registers. In a multiprocessing system, the bus master drives
WR. WR has a 20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0=00x.
Sequential Burst Access. BRST is asserted by ADSP-21161N to indicate that data
associated with consecutive addresses is being read or written. A slave device samples the
initial address and increments an internal address counter after each transfer. The incre-
mented address is not pipelined on the bus. A master ADSP-21161N in a multiprocessor
environment can read slave external port buffers (EPBx) using the burst protocol. BRST is
asserted after the initial access of a burst transfer. It is asserted for every cycle after that,
except for the last data request cycle (denoted by RD or WR asserted and BRST negated).
A keeper latch on the DSP’s BRST pin maintains the input at the level it was last driven.
This latch is only enabled on the ADSP-21161N with ID2–0=00x.
Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to an
external memory access. ACK is used by I/O devices, memory controllers, or other periph-
erals to hold off completion of an external memory access. The ADSP-21161N deasserts
ACK as an output to add wait states to a synchronous access of its IOP registers. ACK has
a 20 kΩ internal pull-up resistor that is enabled during reset or on DSPs with ID2–0=00x.
Suspend Bus and Three-State. External devices can assert SBTS (low) to place the
external bus address, data, selects, and strobes in a high impedance state for the following
cycle. If the ADSP-21161N attempts to access external memory while SBTS is asserted, the
processor will halt and the memory access will not be completed until SBTS is deasserted.
SBTS should only be used to recover from host processor/ADSP-21161N deadlock.
SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx,
and sometimes SDA10, defines the operation for the SDRAM to perform.
SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and
sometimes SDA10, defines the operation for the SDRAM to perform.
SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes
SDA10, defines the operation for the SDRAM to perform.
SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a
precharge command and during SDRAM power-up initialization.
SDRAM Clock Output 0. Clock for SDRAM devices.
SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple
SDRAM devices, handles the increased clock load requirements, eliminating need of off-
chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated.
SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data
sheet supplied with the SDRAM device.
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-
SDRAM accesses or host accesses. This pin replaces the DSP’s A10 pin only during SDRAM
accesses.
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be
either edge-triggered or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or output. As an input, it
can be tested as a condition. As an output, it can be used to signal external peripherals.
Timer Expired. Asserted for four core clock cycles when the timer is enabled and
TCOUNT decrements to zero.
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-
21161N’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-
21161N that is bus master will relinquish the bus and assert HBG. To relinquish the bus,
the ADSP-21161N places the address, data, select, and strobe lines in a high impedance
state. HBR has priority over all ADSP-21161N bus requests (BR6–1) in a multiprocessing
system.
REV. A
–13–
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