ADSP-21161NKCA-100(RevA) データシートの表示（PDF） - Analog Devices

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ADSP-21161NKCA-100
(Rev.:RevA)

DSP Microcomputer

Analog Devices 

ADSP-21161N

Use the exact timing information given. Do not attempt to derive

parameters from the addition or subtraction of others. While

addition or subtraction would yield meaningful results for an

individual device, the values given in this data sheet reflect sta-

tistical variations and worst cases. Consequently, it is not

meaningful to add parameters to derive longer times.

See Figure 40 on Page 51 under Test Conditions for voltage

reference levels.

Switching characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching charac-

teristics describe what the processor will do in a given circum-

stance. Use switching characteristics to ensure that any timing

requirement of a device connected to the processor (such as

memory) is satisfied.

Timing requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input for a

read operation. Timing requirements guarantee that the

processor operates correctly with other devices.

Power Dissipation

Total power dissipation has two components: one due to internal

circuitry and one due to the switching of external output drivers.

Internal power dissipation depends on the instruction execution

sequence and the data operands involved. Using the current spec-

ifications (IDDINPEAK, IDDINHIGH, IDDINLOW, IDDIDLE) from the

Electrical Characteristics on Page 18 and the current-versus-

operation information in Table 6, the programmer can estimate

the ADSP-21161N’s internal power supply (VDDINT) input

current for a specific application, according to the following

formula:

% Peak × IDDINPEAK

% High × IDDINHIGH

% Low × IDDINLOW

+------%-------I--d---l--e----×----I---D----D----I--D----L---E--

IDDINT

Table 6. Operation Types Versus Input Current

Operation

Instruction Type

Instruction Fetch

Core Memory Access2

Internal Memory DMA

External Memory DMA

Data bit pattern for core

memory access and DMA

Peak Activity1

(IDDINPEAK)

Multifunction

Cache

2 per tCK cycle (DM×64 and PM×64)

1 per 2 tCCLK cycles

1 per external port cycle (×32)

Worst case

High Activity1

(IDDINHIGH)

Multifunction

Internal Memory

1 per tCK cycle (DM×64)

1 per 2 tCCLK cycles

1 per external port cycle (×32)

Random

Low Activity1

(IDDINLOW)

Single Function

Internal Memory

None

N/A

N/A

N/A

1 The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.

2 These assume a 2:1 core clock ratio. For more information on ratios and clocks (tCK and tCCLK), see the timing ratio definitions on Page 20.

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

• The number of output pins that switch during each cycle

(O)

• The maximum frequency at which they can switch (f)

• Their load capacitance (C)

• Their voltage swing (VDD)

and is calculated by:

PEXT

=

O

×

C

×

VD

2

D

×

f

The load capacitance should include the processor package

capacitance (CIN). The switching frequency includes driving the

load high and then back low. At a maximum rate of 1/tCK,

address and data pins can drive high and low, while writing to a

SDRAM memory.

Example: Estimate PEXT with the following assumptions:

• A system with one bank of external memory (32 bit)

• Two 1M ؋ 16 SDRAM chips are used, each with a load

of 10 pF (ignoring trace capacitance)

• External Data Memory writes can occur every cycle at a

rate of 1/tCK with 50% of the pins switching

• The bus cycle time is 50 MHz

• The external SDRAM clock rate is 100 MHz

• Ignoring SDRAM refresh cycles

• Addresses are incremental and on the same page

The PEXT equation is calculated for each class of pins that can

drive, as shown in Table 7.

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

Where:

PTOTAL = PEXT + PINT + PPLL

PEXT is from Table 7.

PINT is IDDINT × 1.8 V, using the calculation IDDINT listed in Power

Dissipation on Page 21.

PPLL is AIDD × 1.8 V, using the value for AIDD listed in the Electrical

Characteristics on Page 18.

REV. A

–21–

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