ADSP-21161NKCA-100(RevA) データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
一致するリスト
ADSP-21161NKCA-100 Datasheet PDF : 60 Pages
| |||
ADSP-21161N
Table 2. Pin Function Descriptions (continued)
Pin
Type
Function
RSTOUT1
TCK
TMS
TDI
TDO
TRST
EMU
VDDINT
VDDEXT
AVDD
AGND
GND
NC
O
I
I/S
I/S
O
I/A
O (O/D)
P
P
P
G
G
Reset Out. When RSTOUT is asserted (low), this pin indicates that the core blocks are in
reset. It is deasserted 4080 cycles after RESET is deasserted indicating that the PLL is stable
and locked.
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal
pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ
internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21161N. TRST has a 20 kΩ
internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21161N Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 50 kΩ internal
pull-up resistor.
Core Power Supply. Nominally +1.8 V dc and supplies the DSP’s core processor (14 pins).
I/O Power Supply. Nominally +3.3 V dc. (13 pins).
Analog Power Supply. Nominally +1.8 V dc and supplies the DSP’s internal PLL (clock
generator). This pin has the same specifications as VDDINT, except that added filtering
circuitry is required. See Power Supplies on Page 9.
Analog Power Supply Return.
Power Supply Return. (26 pins).
Do Not Connect. Reserved pins that must be left open and unconnected. (5 pins2).
1 RSTOUT exists only for silicon revision 1.2.
2 Four NC pins for silicon revision 1.2, because RSTOUT has been added.
Table 3. Clock Rate Ratios
CLKDBL
1
1
1
0
0
0
CLK_CFG1
0
0
1
0
0
1
CLK_CFG0
0
1
0
0
1
0
Core:CLKIN
2:1
3:1
4:1
4:1
6:1
8:1
CLKIN:CLKOUT
1:1
1:1
1:1
1:2
1:2
1:2
BOOT MODES
Table 4. Boot Mode Selection
EBOOT
1
0
0
0
0
1
LBOOT
0
0
1
1
0
1
BMS
Output
1 (Input)
0 (Input)
1 (Input)
0 (Input)
x (Input)
Booting Mode
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Serial Boot via SPI
Link Port
No Booting. Processor executes from external memory.
Reserved
REV. A
–17–
Share Link: 