AD7884AN データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

一致するリスト

AD7884AN

LC2MOS 16-Bit, High Speed Sampling ADCs

Analog Devices 

AD7884/AD7885

Timing and Control Section

Figure 9 shows the timing and control sequence for the

AD7884/AD7885. When the part receives a CONVST pulse,

the conversion begins. The input sample-and-hold goes into the

hold mode 50 ns after the rising edge of CONVST and BUSY

goes low. This is the first phase of conversion and takes 3.35 µs

to complete. The second phase of conversion begins when SW2

is turned off and SW3 turned on. The Residue Amplifier and

SHA section (A2 in Figure 8) goes into hold mode at this point

and allows the input sample-and-hold to go back into sample

mode. Thus, while the second phase of conversion is ongoing,

the input sample-and-hold is also acquiring the input signal for

the next conversion. This overlap between conversion and ac-

quisition allows throughput rates of 166 kSPS to be achieved.

CONVST

BUSY

INPUT HOLD

SHA SAMPLE

FIRST PHASE

3.5µs

SECOND

PHASE

1.8µs

TACQ

2.5µs

A1

VINV

±5V IN S

±5V IN F

±3V IN S

±3V IN F

Figure 10. ±5 V Input Range Connection

±5V IN S

±5V IN F

±3V IN S

A1

V INV

±3V IN F

FIRST PHASE OF CONVERSION

1ST 9-BIT CONVERSION

DAC SETTLING TIME

RESIDUE AMPLIFIER

SETTLING TIME

SECOND PHASE OF CONVERSION

2ND 9-BIT CONVERSION

ERROR CORRECTION

OUTPUT LATCH UPDATE

Figure 9. Timing and Control Sequence

USING THE AD7884/AD7885 ANALOG INPUT RANGES

The AD7884/AD7885 can be set up to have either a ± 3 volts

analog input range or a ± 5 volts analog input range. Figures 10

and 11 show the necessary corrections for each of these. The

output code is 2s complement and the ideal code table for both

input ranges is shown in Table I.

Reference Considerations

The AD7884/AD7885 operates from a ± 3 volt reference. This

can be derived simply using the AD780 as shown in Figure 6.

Figure 11. ±3 V Input Range Connections

The critical performance specification for a reference in a 16-bit

application is noise. The reference pk-pk noise should be insig-

nificant in comparison to the ADC noise. The AD7884/

AD7885 has a typical rms noise of 120 µV. For example a rea-

sonable target would be to keep the total rms noise less than

125 µV. To do this the reference noise needs to be less than

35 µV rms. In the 100 kHz band, the AD780 noise is less than

30 µV rms, making it a very suitable reference.

The buffer amplifier used to drive the device VREF+ should have

low enough noise performance so as not to affect the overall

system noise requirement. The AD845 and AD817 achieve

this.

Table I. Ideal Output Code Table for the AD7884/AD7885

In Terms of FSR2

Analog Input

؎3 V Range3

؎5 V Range4

Digital Output

Code Transitionl

+FSR/2 – 1 LSB

+FSR/2 – 2 LSBs

+FSR/2 – 3 LSBs

AGND + 1 LSB

AGND

AGND – 1 LSB

–(FSR/2 – 3 LSBs)

–(FSR/2 – 2 LSBs)

–(FSR/2 – 1 LSB)

2.999908

2.999817

2.999726

0.000092

0.000000

–0.000092

–2.999726

–2.999817

–2.999908

4.999847

4.999695

4.999543

0.000153

0.000000

–0.000153

–4.999543

–4.999695

–4.999847

011 . . . 111 to 111 . . . 110

011 . . . 110 to 011 . . . 101

011 . . . 101 to 011 . . . 100

000 . . . 001 to 000 . . . 000

000 . . . 000 to 111 . . . 111

111 . . . 111 to 111 . . . 110

100 . . . 011 to 100 . . . 010

100 . . . 010 to 100 . . . 001

100 . . . 001 to 100 . . . 000

NOTES

1This table applies for VREF+S = +3 V.

2FSR (Full-Scale Range) is 6 volts for the ± 3 V input range and 10 volts for the ± 5 V input range.

31 LSB on the ± 3 V range is FSR/216 and is equal to 91.5 µV.

41 LSB on the ± 5 V range is FSR/216 and is equal to 152.6 µV.

REV. C

–9–

Share Link: