AD7884AN データシートの表示（PDF） - Analog Devices

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AD7884AN

LC2MOS 16-Bit, High Speed Sampling ADCs

Analog Devices 

AD7884/AD7885

Decoupling and Grounding

The AD7884 and AD7885A have one AVDD pin and two VDD

pins. They also have one AVSS pin and three VSS pins. The

AD7885 has one AVDD pin, one VDD pin, one AVSS pin and one

VSS pin. Figure 6 shows how a common +5 V supply should be

used for the positive supply pins and a common –5 V supply for

the negative supply pins.

For decoupling purposes, the critical pins on both devices are

the AVDD and AVSS pins. Each of these should be decoupled to

system AGND with 10 µF tantalum and 0.1 µF ceramic capaci-

tors right at the pins. With the VDD and VSS pins, it is sufficient

to decouple each of these with ceramic 1 µF capacitors.

AGNDS, AGNDF are the ground return points for the on-chip

9-bit ADC. They should be driven by a buffer amplifier as

shown in Figure 6. If they are tied directly together and then

to ground, there will he a marginal degradation in linearity

performance.

The GND pin is the analog ground return for the on-chip linear

circuitry. It should he connected to system analog ground.

The DGND pin is the ground return for the on-chip digital

circuitry. It should be connected to the ground terminal of the

VDD and VSS supplies. If a common analog supply is used for

AVDD and VDD then DGND should be connected to the com-

mon ground point.

Power Supply Sequencing

AVDD and VDD are connected to a common substrate and there

is typically 17 Ω resistance between them. If they are powered

by separate +5 V supplies, then these should come up simulta-

neously. Otherwise, the one that comes up first will have to

drive +5 V into a 17 Ω load for a short period of time. However,

the standard short-circuit protection on regulators like the 7800

series will ensure that there is no possibility of damage to the

driving device.

AVSS should always come up either before or at the same time

as VSS. If this cannot be guaranteed, Schottky diodes should be

used to ensure that VSS never exceeds AVSS by more than 0.3 V.

Arranging the power supplies as in Figure 6 and using the recom-

mended decoupling ensures that there are no power supply

sequencing issues as well as giving the specified noise performance.

+5V

+5V

–5V

–5V

AVDD VDD

AVSS

VSS

HP5082-2810

OR

EQUIVALENT

AD7884/AD7885

Figure 12. Schottky Diodes Used to Protect Against

Incorrect Power Supply Sequencing

AD7884/AD7885 PERFORMANCE

Linearity

The linearity of the AD7884/AD7885 is determined by the

on-chip 16-bit D/A converter. This is a segmented DAC which

is laser trimmed for 16-bit DNL performance to ensure that

there are no missing codes in the ADC transfer function. Figure

13 shows a typical INL plot for the AD7884/AD7885.

2.0

VDD = +5V

1.5

VSS = –5V

TA = +25°C

1.0

0.5

0

0

16384

32768

49152

65535

OUTPUT CODE

Figure 13. AD7884/AD7885 Typical Linearity Performance

Noise

In an A/D converter, noise exhibits itself as code uncertainty in

dc applications and as the noise floor (in an FFT, for example)

in ac applications.

In a sampling A/D converter like the AD7884/AD7885, all in-

formation about the analog input appears in the baseband from

dc to 1/2 the sampling frequency. An antialiasing filter will re-

move unwanted signals above fS/2 in the input signal but the

converter wideband noise will alias into the baseband. In the

AD7884/AD7885, this noise is made up of sample-and-hold

noise and A/D converter noise. The sample-and-hold section

contributes 51 µV rms and the ADC section contributes 59 µV

rms. These add up to a total rms noise of 78 µV. This is the in-

put referred noise in the ± 3 V analog input range. When operat-

ing in the ± 5 V input range, the input gain is reduced to –0.6.

This means that the input referred noise is now increased by a

factor of 1.66 to 120 µV rms.

Figure 14 shows a histogram plot for 5000 conversions of a dc

input using the AD7884/AD7885 in the ± 5 V input range. The

analog input was set as close as possible to the center of a code

transition. All codes other than the center code are due to the

ADC noise. In this case, the spread is six codes.

3000

2000

1000

0

(X – 2) (X – 1) (X) (X + 1) (X + 2) (X + 3)

CODE

Figure 14. Histogram of 5000 Conversions of a DC Input

–10–

REV. C

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