82443MX データシートの表示（PDF） - Intel

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82443MX

82443MX PCIset

Intel 

82443MX PCIset

7.9.6.2

RTC Battery ............................................................................................ 115

7.9.7 Century Rollover ........................................................................................................... 115

7.10 Interrupt Controller...................................................................................................................... 115

7.10.1 Interrupt Controller Functional Description .................................................................... 116

7.10.1.1 Interrupt Sequence.................................................................................. 118

7.10.1.2 Interrupt Acknowledge Cycle................................................................... 119

7.10.1.3 Programming the Interrupt Controller ...................................................... 120

7.10.1.4 End-of-Interrupt Operation....................................................................... 123

7.10.1.5 Register Functionality.............................................................................. 126

7.10.1.6 Interrupt Masks ....................................................................................... 127

7.10.1.7 Reading the Interrupt Controller Status ................................................... 127

7.10.1.8 Interrupt Steering .................................................................................... 128

7.10.2 Serial IRQ Scheme ....................................................................................................... 130

7.10.2.1 Overview................................................................................................. 130

7.10.2.2 Protocol................................................................................................... 130

7.10.2.3 SMI# Via SERIRQ................................................................................... 132

7.10.2.4 SERIRQ ORing with ISA IRQ.................................................................. 132

7.11 USB Host Controller ................................................................................................................... 132

7.12 IDE Interface .............................................................................................................................. 133

7.12.1 ATA Register Block Decode.......................................................................................... 134

7.12.2 PIO IDE Transactions ................................................................................................... 136

7.12.3 PIO IDE Timing Modes ................................................................................................. 136

7.12.4 Enhanced Timing Modes .............................................................................................. 138

7.12.4.1 PIORDY Masking .................................................................................... 139

7.12.4.2 PIO 32-Bit IDE Data Port Accesses ........................................................ 139

7.12.4.3 PIO IDE Data Port Prefetching and Posting ............................................ 139

7.12.5 Bus Master Function ..................................................................................................... 139

7.12.5.1 Physical Region Descriptor Format ......................................................... 139

7.12.5.2 Operation ................................................................................................ 140

7.12.6 “Ultra DMA/33” Synchronous DMA Operation ............................................................... 141

7.12.6.1 Signal Descriptions ................................................................................. 141

7.12.6.2 Operation ................................................................................................ 142

7.12.6.3 CRC Calculation...................................................................................... 142

7.12.6.4 Reference ............................................................................................... 142

7.13 X-bus .......................................................................................................................................... 143

7.13.1 Target I/O Interface....................................................................................................... 143

7.13.2 X-bus Clock (SYSCLK) Generation............................................................................... 144

7.13.3 Wait State and Shortened Cycle Generation................................................................. 144

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