82443MX データシートの表示（PDF） - Intel

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82443MX

82443MX PCIset

Intel 

82443MX PCIset

Table 36. Host Bus Transactions Supported .................................................................................................. 53

Table 37. Host Bus Responses Supported ..................................................................................................... 54

Table 38. Special Cycle Transactions............................................................................................................. 55

Table 39. Events Causing INIT# Active .......................................................................................................... 58

Table 40. Sample Of Possible Options for 6 Row/3 DIMM Configurations ...................................................... 60

Table 41. Data Bytes on DIMM Used for Programming DRAM Registers ....................................................... 62

Table 42. Command Truth Table .................................................................................................................... 63

Table 43. DQM Truth Table ............................................................................................................................ 64

Table 44. Operative Command Table ............................................................................................................. 64

Table 45. MA Muxing vs. DRAM Address Split............................................................................................... 69

Table 46. Programmable SDRAM Timing Parameters.................................................................................... 70

Table 47. Available Memory for SMRAM when Extended SMRAM Enabled................................................... 74

Table 48. Extended SMRAM DRAM Memory Regions ................................................................................... 75

Table 49. SMRAM Range Decode.................................................................................................................. 77

Table 50. SMRAM Decode Control................................................................................................................. 77

Table 51. AC’97 Audio Pin Description........................................................................................................... 79

Table 52. Supported Data Streams ................................................................................................................ 81

Table 53. PCI Commands Supported by the North Bridge/Cluster when Acting as a PCI Target.................... 83

Table 54. PCI Commands Supported by North Bridge/Cluster when Acting as a PCI Initiator ........................ 85

Table 55. PCI Commands Supported by the South Bridge/Cluster when Acting as a PCI Target ................... 87

Table 56. PCI Commands Supported by the South Bridge/Cluster when Acting as a PCI Initiator.................. 88

Table 57. Rotating Priority Example ............................................................................................................... 94

Table 58. DMA Transfer Size ......................................................................................................................... 95

Table 59. Address Shifting in 16-bit I/O DMA Transfers ................................................................................. 95

Table 60. Terminal Count Summary .............................................................................................................. 97

Table 61. DMA Cycle vs. I/O Address .......................................................................................................... 100

Table 62. PCI Data Bus vs. DMA I/O Port Size ............................................................................................ 101

Table 63. DMA I/O Cycle Width vs. BE[3:0]#................................................................................................ 101

Table 64. 8237 Registers and DDMA Function............................................................................................. 103

Table 65. Mapping the 8237 Register to DDMA Peripheral........................................................................... 106

Table 66. Interval Timer Functions ............................................................................................................... 109

Table 67. Interval Timer Counters I/O Address Map..................................................................................... 109

Table 68. Counter Operating Modes............................................................................................................. 111

Table 69. Interrupt Controller Register I/O Port Address Map....................................................................... 118

Table 70. Typical Interrupt Functions............................................................................................................ 118

Table 71. Content of Interrupt Vector Byte for 80x86 System Mode ............................................................. 120

Table 72. Suggested Default Values for ICW Registers................................................................................ 121

Table 73. SIRQ Frames................................................................................................................................ 131

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