82443MX データシートの表示（PDF） - Intel
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82443MX Datasheet PDF : 173 Pages
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82443MX PCIset
6.2.2.3
PCI Memory Address Range (Top of Main Memory to 4 GB) .................... 44
6.2.2.4
High BIOS Area (FFC0_0000h - FFFF_FFFFh) ........................................ 44
6.3 System Management Mode (SMM) Memory Range ..................................................................... 44
6.4 Memory Shadowing ...................................................................................................................... 45
6.5 Decode Rules and Cross-Bridge Address Mapping ...................................................................... 45
6.5.1 PCI Interface Memory Decode Rules.............................................................................. 45
6.5.2 Legacy VGA Range ........................................................................................................ 45
6.6 I/O Address Space ....................................................................................................................... 45
6.6.1 Fixed I/O Address Ranges .............................................................................................. 46
6.6.2 Variable I/O Decode Ranges .......................................................................................... 50
7. FUNCTIONAL DESCRIPTION ............................................................................................................... 53
7.1 Mobile Celeron™ Processor / Pentium® II Processor Host Interface............................................ 53
7.1.1 Overview......................................................................................................................... 53
7.1.2 Host Bus Device Support................................................................................................ 53
7.1.3 Special cycles................................................................................................................. 55
7.1.4 Symmetric Multiprocessor (SMP) Configuration.............................................................. 56
7.1.5 In-Order Queue Pipelining .............................................................................................. 56
7.1.6 Frame Buffer Memory Support (USWC).......................................................................... 56
7.1.7 CPU Sideband Interface ................................................................................................. 57
7.1.7.1
A20M# ...................................................................................................... 57
7.1.7.2
FERR# / IGNNE# (Coprocessor Error)...................................................... 57
7.1.7.3
INIT# ......................................................................................................... 58
7.1.7.4
Interrupt Signals ........................................................................................ 58
7.1.7.5
NMI ........................................................................................................... 58
7.1.7.6
SMI# ......................................................................................................... 58
7.1.7.7
STPCLK# .................................................................................................. 58
7.2 Memory Interface.......................................................................................................................... 59
7.2.1 DRAM Interface .............................................................................................................. 59
7.2.1.1
DRAM Interface Overview......................................................................... 59
7.2.2 DRAM Organization and Configuration ........................................................................... 59
7.2.2.1
Configuration Mechanism for DIMMs ........................................................ 61
7.2.3 SDRAM Cycle Encoding ................................................................................................. 63
7.2.4 DRAM Address Translation and Decoding ...................................................................... 68
7.2.5 SDRAMC Register Programming.................................................................................... 69
7.2.6 SDRAM Paging Policy .................................................................................................... 70
7.2.6.1
Overview................................................................................................... 70
7.2.6.2
Open Page Arbitration Policies.................................................................. 70
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