82443MX データシートの表示（PDF） - Intel

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82443MX

82443MX PCIset

Intel 

82443MX PCIset

List of Tables

PAGE

Table 1. Main Feature Set ................................................................................................................................ 1

Table 2. Host Interface Signal Description........................................................................................................ 8

Table 3. Memory I/F Signal Description......................................................................................................... 11

Table 4. IDE Signal Description...................................................................................................................... 12

Table 5. Other System/Test Signal Description .............................................................................................. 13

Table 6. PCI I/F Signal Description................................................................................................................. 13

Table 7. AC’97 Signal Description ................................................................................................................ 15

Table 8. Interrupt Signal Description.............................................................................................................. 16

Table 9. RTC Signal Description..................................................................................................................... 16

Table 10. Clocks, Reset, PLLs and Miscellaneous Signal Description............................................................ 16

Table 11. USB Signal Description................................................................................................................... 17

Table 12. SMBus Signal Description .............................................................................................................. 17

Table 13. Power Management Signal Description .......................................................................................... 17

Table 14. GPIO Signal Description ................................................................................................................ 19

Table 15. X-bus Signal Description................................................................................................................ 19

Table 16. Core Power Pins............................................................................................................................. 22

Table 17. Host I/F Power Pins ........................................................................................................................ 22

Table 18. RTC Power Pins ............................................................................................................................. 23

Table 19. USB Power Pins ............................................................................................................................. 23

Table 20. Resume Power Pins ....................................................................................................................... 23

Table 21. VREF Power Pins ........................................................................................................................... 23

Table 22. GPIO Pins Programmed through Config. Dev.7, Fn. 0.................................................................... 23

Table 23. System Resume with GPIO Signals Programmed as Functional Pins ............................................ 25

Table 24. Power-On Reset Values by Signal Group ....................................................................................... 27

Table 25. DRAM Interface Signals................................................................................................................. 33

Table 26. Miscellaneous Signals .................................................................................................................... 34

Table 27. Power-Up Options During Reset ..................................................................................................... 36

Table 28. Mobile Celeron™ Processor / Pentium® II Processor Frequency Ratios ........................................ 37

Table 29. Power Planes ................................................................................................................................. 38

Table 30. RTC Well Signals............................................................................................................................ 38

Table 31. Resume Well Signals...................................................................................................................... 39

Table 32. Memory Segment Attributes ........................................................................................................... 41

Table 33. Compatibility Memory Area............................................................................................................. 42

Table 34. Fixed I/O Ranges Decoded by the 440MX ...................................................................................... 46

Table 35. Variable I/O Decode Ranges (Available I/O Space is 0 - 64KB)...................................................... 51

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