MT28S4M16LCTG-10 データシートの表示（PDF） - Micron Technology

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MT28S4M16LCTG-10

SYNCFLASH® MEMORY

Micron Technology 

subsequent WRITE command (WRITE commands

must be preceded by LCR/ACTIVE), and data from a

fixed-length READ burst may be immediately followed

by data from a subsequent WRITE command (subject

to bus turnaround limitations). The WRITE may be

initiated on the clock edge immediately following the

last (or last desired) data element from the READ burst,

provided that I/O contention can be avoided. In a given

system design, there may be the possibility that the

device driving the input data would go Low-Z before

the SyncFlash memory DQs go High-Z. In this case, at

least a single-cycle delay should occur between the last

read data and the WRITE command.

The DQM input is used to avoid I/O contention as

shown in Figure 9. The DQM signal must be asserted

(HIGH) at least two clocks prior to the WRITE command

(DQM latency is two clocks for output buffers) to sup-

press data-out from the READ. Once the WRITE com-

mand is registered, the DQs will go High-Z (or remain

4 MEG x 16

SYNCFLASH MEMORY

High-Z) regardless of the state of the DQM signal. The

DQM signal must be de-asserted prior to the WRITE

command (DQM latency is zero clocks for input buff-

ers) to ensure that the written data is not masked. Fig-

ure 9 shows the case where the clock frequency allows

for bus contention to be avoided without adding a NOP

cycle.

A fixed-length or full-page READ burst can be trun-

cated with ACTIVE TERMINATE (may or may not be

bank specific) or BURST TERMINATE (not bank spe-

cific). The ACTIVE TERMINATE or BURST TERMINATE

command should be issued x cycles before the clock

edge at which the last desired data element is valid,

where x equals the CAS latency minus one. This is

shown in Figure 10 for each possible CAS latency; data

element n + 3 is the last desired data element of a burst

of four or the last desired of a longer burst.

T0

T1

T2

T3

T4

CLK

DQM, H

COMMAND

READ

LCR

ACTIVE

NOP

WRITE

ADDRESS

BANK,

COL n

40h

DQ

BANK

ROW

tCK

tHZ

BANK,

COL b

DOUT n

DIN b

tDS

NOTE:

A CAS latency of three is used for illustration. The

READ command may be to any bank, and the WRITE

command may be to any bank. If a CAS latency of one is

used, then DQM is not required.

DON’T CARE

Figure 9

READ to WRITE

4 Meg x 16 SyncFlash

MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01

18

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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