SST38VF166-70-4C-EK データシートの表示（PDF） - Silicon Storage Technology

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SST38VF166-70-4C-EK

16 Megabit FlashBank Memory

Silicon Storage Technology 

16 Megabit FlashBank Memory

SST38VF166

Data Sheet

be no issue when recovering from the system reset. See

Table 6 or 7 for the specific codes and Figure 40 for a timing

waveform.

There is no provision to abort an Erase, Program, or Write

operation, once initiated. For the SST SuperFlash technol-

ogy, the associated Erase, Program, and Write times are

so fast, relative to system reset times, there is no value in

aborting the operation. Note, reads can always occur from

any bank not performing an Erase, Program, or Write oper-

ation.

Should the system reset, while a Block- or Sector-Erase or

Word-Program is in progress in the bank where the boot

code is stored, the system must wait for the completion of

the operation before reading that bank. Since the maxi-

mum time the system would have to wait is 25 ms (for a

Block-Erase), the system ability to read the boot code

would not be affected.

Data# Polling (DQ7) - Flash Bank

When the SST38VF166 is in the internal Flash bank Pro-

gram cycle, any attempt to read DQ7 of the last word

loaded during the Flash bank Word Load cycle will receive

the complement of the true data. Once the Write cycle is

completed, DQ7 will show true data. The device is then

ready for the next operation. See Figure 21 or 22 for the

Flash bank Data Polling timing waveforms and Figure 51

for a flowchart.

Data# Polling (DQ7) - E2 Bank

When the SST38VF166 is in the internal E2 bank Write

cycle, any attempt to read DQ7 of the last word loaded dur-

ing the E2 bank Word Load cycle will receive the comple-

ment of the true data. Once the Write cycle is completed,

DQ7 will show true data. The device is then ready for the

next operation. See Figure 23 for E2 bank Data Polling tim-

ing waveforms and Figure 51 for a flowchart.

Toggle Bit (DQ6) - Flash Bank

During the Flash bank internal Write cycle, any consecutive

attempts to read DQ6 will produce alternating 0s and 1s,

i.e. toggling between 0 and 1. When the Write cycle is com-

pleted, the toggling will stop. The device is then ready for

the next operation. See Figure 24 or 25 for Flash bank Tog-

gle Bit timing waveforms and Figure 51 for a flowchart.

Toggle Bit (DQ6) - E2 Bank

During the E2 bank internal Write cycle, any consecutive

attempts to read DQ6 will produce alternating 0s and 1s,

i.e. toggling between 0 and 1. When the Write cycle is com-

pleted, the toggling will stop. The device is then ready for

the next operation. See Figure 26 for E2 bank Toggle Bit

timing waveforms and Figure 51 for a flowchart.

Data Protection

The SST38VF166 provides both hardware and software

features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# pulse of less than 5 ns will

not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5 volts.

Write Inhibit Mode: Forcing OE# low, BE#1 and BE#2 high,

or WE# high will inhibit the Write operation to the Flash

bank. Forcing OE# low, BE#3 high, or WE# high will inhibit

the Write operation to the E2 bank. This prevents inadvert-

ent writes during power-up or power-down.

A One Time Programmable E2 Sector

The first sector of the E2 bank offers the option of OTP

(One Time Programmable) prevention of write for the first

sector, i.e., addresses A5 to A13 are “0” (0000H to 001FH).

Once the OTP software instruction is executed, no Write,

Erase, or Program operation can be performed on these 32

words. This is permanent and non-reversible. Additionally, if

the OTP prevention is enabled, the Bank-Erase for the E2

bank will not function. See Table 7 for specific codes and

Figure 39 for a timing waveform.

Software Data Protection (SDP)

The SST38VF166 provides the JEDEC approved Software

Data Protection scheme as a requirement for initiating a

Write, Erase, or Program operation. With this scheme, any

Write operation requires the inclusion of a series of three

word-load operations to precede the Word-Write or Word-

Program operation. The three-word load sequence is used

to initiate the Write or Program cycle, providing optimal pro-

tection from inadvertent Write operations, e.g., during the

system power-up or power-down. The six-word sequence

is required to initiate any Bank-, Block-, or Sector-Erase

operation.

©2001 Silicon Storage Technology, Inc.

5

327-3 2/01

S71065

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