SST38VF166-70-4C-EK データシートの表示（PDF） - Silicon Storage Technology

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SST38VF166-70-4C-EK

16 Megabit FlashBank Memory

Silicon Storage Technology 

16 Megabit FlashBank Memory

SST38VF166

Data Sheet

subsequent bus cycle, when WE# is low, in the SDP com-

mand sequence, the device will abort the attempted SDP

command and revert to the Read mode. Note, the SDP

command sequence may be suspended by taking WE#

high. A different BE# may then be pulsed to read from

either of the banks not involved with the SDP command

sequence.

For the purposes of simplification, the following descrip-

tions will assume WE# is toggled to initiate an Erase, Pro-

gram, or Write. Toggling the applicable BE# will accomplish

the same function. Note, there are separate timing dia-

grams to illustrate both WE# and BE# controlled Program

or Write commands.

Flash Bank Word-Program

The Flash bank Word-Program operation consists of issu-

ing the SDP Word-Program command, initiated by forcing

BE#1 or BE#2 and WE# low, and OE# high. The words to

be programmed must be in the erased state, prior to pro-

gramming. The Word-Program command programs the

desired addresses word-by-word. During the Word-Pro-

gram cycle, the addresses are latched by the falling edge of

WE#. The data is latched by the rising edge of WE#. See

Figure 5 or 7 for WE# or 6 and 8 for BE# controlled Word-

Program cycle timing waveforms, Table 6 for the command

sequence, and Figure 49 for a flowchart.

During the Flash bank Erase or Program operation, the

only valid reads from that bank are Data# Polling and Tog-

gle Bit. The other Flash bank or the E2 bank may be read.

The specified Bank-, Block-, or Sector-Erase time is the

only time required to erase. There are no preprogramming

or other commands or cycles required either internally or

externally to erase the bank, block, or sector.

E2 Bank Word-Write

The E2 bank Word-Write operation consists of issuing the

SDP command, initiated by forcing BE#3 and WE# low,

and OE# high; followed by the Word Load cycle to the

SST38VF166. The internally controlled Write cycle stores

the data loaded in the word buffer into the E2 bank. The

address selected is then erased and programmed, by inter-

nally controlled signals. During the Word Load cycle, the

address is latched by the falling edge of WE#. The data is

latched by the rising edge of WE#. The internal write cycle

is initiated on the rising edge of WE#. The Write cycle, once

initiated, will continue to completion, typically within 7 ms.

See Figure 9 for WE# or 10 for BE# controlled write cycle

timing waveforms, Table 7 for the command sequence, and

Figure 48 for a flowchart.

The Write operation has two functional cycles: the Word

Load cycle and the internal Write cycle. The Word Load

cycle consists of loading 1 word of data into the word buffer

at the completion of the SDP sequence. The internal Write

cycle consists of the write timer operation, to erase and

program the selected address. Note, the word does NOT

have to be erased prior to writing. During the Write opera-

tion, the only valid reads are Data# Polling and Toggle Bit

from the E2 bank or normal read from either of the Flash

banks.

E2 Bank Word-Program

The E2 bank Word-Program operation consists of issuing

the SDP Word-Program command, initiated by forcing

BE#3 and WE# low and OE# high. The Word-Program

command programs the desired addresses word-by-word.

The words to be programmed must be in the erased state,

prior to programming, unlike the Word-Write operation.

During the Word-Program cycle, the addresses are latched

by the falling edge of WE#. The data is latched by the rising

edge of WE#. See Figure 11 for WE# or 12 for BE#3 con-

trolled Program cycle timing waveforms, Table 7 for the

command sequence and Figure 50 for a flowchart.

During the E2 bank Erase or Program operation, the only

valid reads from the bank are Data# Polling and Toggle Bit.

Either Flash bank may be read.

The specified Bank- or Sector-Erase time is the only time

required to erase. There are no preprogramming or other

commands or cycles required either internally or externally

to erase the bank or sector.

Erase Operations

The Bank-Erase is initiated by a specific six-word load

sequence See Tables 6 and 7. A Bank-Erase will typically

be less than 70 ms.

An alternative to the Bank-Erase in the Flash bank is the

Block-Erase or Sector-Erase. The Block-Erase will erase

an entire Block (32 KWords) in typically 15 ms. The Sector-

Erase will erase an entire sector (1024 words) in typically

15 ms. The Sector-Erase provides a means to alter a sin-

gle sector using the Sector-Erase and Word-Program

modes. The Sector-Erase is initiated by a specific six-word

load sequence, see Table 6.

The E2 bank may also use a Sector-Erase, instead of

Bank-Erase. An E2 bank sector consists of 32 words that

will typically erase in 7 ms. The Sector-Erase is initiated by

a specific six-word load sequence, see Table 7. Sector- or

Bank-Erase and Word-Program is an alternative to Word-

Write as a means to alter the E2 bank.

©2001 Silicon Storage Technology, Inc.

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