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NQ6311 データシートの表示(PDF) - Unspecified

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NQ6311 Datasheet PDF : 902 Pages
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25.5
25.4.11 HEADTYP – Header Type Register (Bn:F4) ............................................. 856
25.4.12 Base Address Registers (Bn:F4) ........................................................... 857
25.4.13 SVID – Subsystem Vendor Identification(Bn:F4)..................................... 859
25.4.14 SID – Subsystem Identification (Bn:F4) ................................................ 859
25.4.15 CAP_PTR – Capabilities Pointer (Bn:F4)................................................. 859
25.4.16 INT_LN – Interrupt Line Register (Bn:F4) .............................................. 859
25.4.17 INT_PN – Interrupt Pin Register (Bn:F4) ............................................... 859
25.4.18 MIN_GNT – Minimum Grant Register (Bn:F4) ......................................... 860
25.4.19 MAX_LAT – Maximum Latency Register (Bn:F4) ..................................... 860
25.4.20 CAP_ID – Capability Identification Register (Bn:F4) ................................ 860
25.4.21 NXT_PTR – Next Item Pointer (Bn:F4) .................................................. 860
25.4.22 PM_CAP – Power Management Capabilities (Bn:F4)................................. 860
25.4.23 PMCSR – Power Management Control/Status Register
(Bn:F4) ............................................................................................ 861
25.4.24 PCIDATA – PCI Power Management Data Register (Bn:F4)....................... 861
25.4.25 MSI_CAP_ID – Capability Identification Register (Bn:F4) ......................... 862
25.4.26 MSI_NXT_PTR – Next Item Pointer (Bn:F4) ........................................... 862
25.4.27 MSI_MCR – Message Control Register (Bn:F4) ....................................... 862
25.4.28 MSI_MAR_LOW – Message Address Low Register (Bn:F4) ........................ 862
25.4.29 MSI_MAR_HIGH – Message Address High Register (Bn:F4) ...................... 863
25.4.30 MSI_MDR – Message Data Register (Bn:F4)........................................... 863
25.4.31 PCI Express_CAP_ID – PCI Express* Capability
Identification Register (Bn:F4) ............................................................. 863
25.4.32 PCI Express_NXT_PTR – PCI Express* Next Item Pointer (Bn:F4) ............. 863
25.4.33 PCI Express_CAP – PCI Express* Capability Register (Bn:F4) ................... 863
25.4.34 PCI Express_DEV_CAP – PCI Express* Device
Capability Register (Bn:F4) ................................................................. 864
25.4.35 PCI Express_DEV_CONT – PCI Express* Device
Control Register (Bn:F4) ..................................................................... 864
25.4.36 PCI Express_DEV_STATUS – PCI Express* Device
Status Register (Bn:F4) ...................................................................... 865
25.4.37 PCI Express_LINK_CAP – PCI Express* Link
Capability Register (Bn:F4) ................................................................. 865
25.4.38 PCI Express_LINK_CONT – PCI Express* Link
Control Register (Bn:F4) ..................................................................... 866
25.4.39 PCI Express_LINK_STATUS – PCI Express* Link
Status Register (Bn:F4) ...................................................................... 866
UHCI Redirection Controller Configuration Registers (Bn:F5).................................. 867
25.5.1 VID – Vendor Identification Register (Bn:F0/F1)..................................... 868
25.5.2 DID – Device Identification Register (Bn:F5).......................................... 868
25.5.3 PCICMD – PCI Command Register (Bn:F5)............................................. 869
25.5.4 PCISTS – PCI Status Register (Bn:F5)................................................... 869
25.5.5 RID – Revision Identification Register (Bn:F5)........................................ 870
25.5.6 PI – Programming Interface Register (Bn:F5)......................................... 871
25.5.7 SCC – Sub Class Code Register (Bn:F5) ................................................ 871
25.5.8 BCC – Base-Class Code Register (Bn:F5)............................................... 871
25.5.9 CLS – Cache Line Size Register (Bn:F5) ................................................ 871
25.5.10 PMLT – Primary Master Latency Timer Register (Bn:F5)........................... 871
25.5.11 HEADTYP – Header Type Register (Bn:F5) ............................................. 871
25.5.12 Base Address Registers (Bn:F5) ........................................................... 872
25.5.13 SVID – Subsystem Vendor Identification(Bn:F5)..................................... 873
25.5.14 SID – Subsystem Identification (Bn:F5) ................................................ 874
25.5.15 CAP_PTR – Capabilities Pointer (Bn:F5)................................................. 874
25.5.16 INT_LN – Interrupt Line Register (Bn:F5) .............................................. 874
25.5.17 INT_PN – Interrupt Pin Register (Bn:F5) ............................................... 874
25.5.18 MIN_GNT – Minimum Grant Register (Bn:F5) ......................................... 874
25.5.19 MAX_LAT – Maximum Latency Register (Bn:F5) ..................................... 874
28
Intel® 631xESB/632xESB I/O Controller Hub Datasheet

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