NQ6311 データシートの表示（PDF） - Unspecified

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NQ6311

Intel® 631xESB/632xESB I/O Controller Hub

Unspecified 

21.4

21.5

21.6

21.7

21.8

21.9

21.3.1 TCW – Timer Control Word Register (LPC I/F – D31:F0).......................... 684

21.3.2 SBYTE_FMT – Interval Timer Status Byte Format Register

(LPC I/F – D31:F0) ............................................................................ 685

21.3.3 Counter Access Ports Register (LPC I/F – D31:F0).................................. 686

8259 Interrupt Controller (PIC) Registers

(LPC I/F – D31:F0) .......................................................................................... 686

21.4.1 Interrupt Controller I/O MAP (LPC I/F – D31:F0) .................................... 686

21.4.2 ICW1 – Initialization Command Word 1 Register

(LPC I/F – D31:F0) ............................................................................ 687

21.4.3 ICW2 – Initialization Command Word 2 Register

(LPC I/F – D31:F0) ............................................................................ 688

21.4.4 ICW3 – Master Controller Initialization Command

Word 3 Register (LPC I/F – D31:F0) ..................................................... 688

21.4.5 ICW3 – Slave Controller Initialization Command

Word 3 Register (LPC I/F – D31:F0) ..................................................... 689

21.4.6 ICW4 – Initialization Command Word 4 Register

(LPC I/F – D31:F0) ............................................................................ 689

21.4.7 OCW1 – Operational Control Word 1 (Interrupt Mask)

Register (LPC I/F – D31:F0) ................................................................ 689

21.4.8 OCW2 – Operational Control Word 2 Register

(LPC I/F – D31:F0) ............................................................................ 690

21.4.9 OCW3 – Operational Control Word 3 Register

(LPC I/F – D31:F0) ............................................................................ 690

21.4.10 ELCR1 – Master Controller Edge/Level Triggered Register

(LPC I/F – D31:F0) ............................................................................ 691

21.4.11 ELCR2 – Slave Controller Edge/Level Triggered Register

(LPC I/F – D31:F0) ............................................................................ 692

Advanced Programmable Interrupt Controller (APIC)(D31:F0) ............................... 692

21.5.1 APIC Register Map (LPC I/F – D31:F0).................................................. 692

21.5.2 IND – Index Register (LPC I/F – D31:F0) .............................................. 693

21.5.3 DAT – Window Register (LPC I/F – D31:F0)........................................... 693

21.5.4 EOIR – EOI Register (LPC I/F – D31:F0) ............................................... 693

21.5.5 ID – Identification Register (LPC I/F – D31:F0) ...................................... 694

21.5.6 VER – Version Register (LPC I/F – D31:F0) ........................................... 694

21.5.7 REDIR_TBL – Redirection Table (LPC I/F – D31:F0) ................................ 695

Real Time Clock Registers (LPC I/F – D31:F0) ..................................................... 696

21.6.1 I/O Register Address Map (LPC I/F – D31:F0)........................................ 696

21.6.2 Indexed Registers (LPC I/F – D31:F0) .................................................. 697

Processor Interface Registers (LPC I/F – D31:F0) ................................................ 700

21.7.1 NMI_SC – NMI Status and Control Register

(LPC I/F – D31:F0) ............................................................................ 700

21.7.2 NMI_EN – NMI Enable (and Real Time Clock Index)

Register (LPC I/F – D31:F0) ................................................................ 701

21.7.3 PORT92 – Fast A20 and Init Register (LPC I/F – D31:F0) ........................ 701

21.7.4 COPROC_ERR – Coprocessor Error Register

(LPC I/F – D31:F0) ............................................................................ 702

21.7.5 RST_CNT – Reset Control Register (LPC I/F – D31:F0)............................ 702

Power Management Registers (PM – D31:F0) ...................................................... 702

21.8.1 Power Management PCI Configuration Registers

(PM – D31:F0) .................................................................................. 702

21.8.2 Power Management I/O Registers ........................................................ 708

System Management TCO Registers (D31:F0) ..................................................... 722

21.9.1 TCO Register I/O Map ........................................................................ 722

21.9.2 TCO_RLD – TCO Timer Reload and Current Value Register ...................... 723

21.9.3 TCO_DAT_IN – TCO Data In Register ................................................... 723

21.9.4 TCO_DAT_OUT – TCO Data Out Register............................................... 723

21.9.5 TCO1_STS – TCO1 Status Register....................................................... 723

21.9.6 TCO2_STS – TCO2 Status Register....................................................... 725

Intel® 631xESB/632xESB I/O Controller Hub Datasheet

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