NQ6311 データシートの表示（PDF） - Unspecified
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NQ6311 Datasheet PDF : 902 Pages
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23.2
23.3
23.1.32 MD – Message Signaled Interrupt Message Data Register
(SATA–D31:F2) ................................................................................. 762
23.1.33 MAP – Port Mapping Register (SATA–D31:F2) ........................................ 763
23.1.34 PCS – Port Control and Status Register (SATA–D31:F2) .......................... 763
23.1.35 SATACR0 – Capability Register 0 (SATA–D31:F2) ................................... 764
23.1.36 SATACR1 – Capability Register 1 (SATA–D31:F2) ................................... 765
23.1.37 ATC – APM Trapping Control Register (SATA–D31:F2) ............................. 765
23.1.38 ATS – APM Trapping Status Register (SATA–D31:F2) .............................. 765
23.1.39 SP Scratch Pad Register (SATA–D31:F2) ............................................... 766
23.1.40 BFCS – BIST FIS Control/Status Register (SATA–D31:F2)........................ 766
23.1.41 BFTD1 – BIST FIS Transmit Data1 Register (SATA–D31:F2)..................... 767
23.1.42 BFTD2 – BIST FIS Transmit Data2 Register (SATA–D31:F2)..................... 767
Bus Master IDE I/O Registers (D31:F2)............................................................... 768
23.2.1 BMIC[P,S] – Bus Master IDE Command Register (D31:F2) ....................... 768
23.2.2 BMIS[P,S] – Bus Master IDE Status Register (D31:F2) ............................ 769
23.2.3 BMID[P,S] – Bus Master IDE Descriptor Table Pointer
Register (D31:F2) .............................................................................. 770
23.2.4 BMINDEX[P,S] – Bus Master Indirect AHCI Index Register
Register (D31:F2) .............................................................................. 770
23.2.5 BMDATA[P,S] – Bus Master Indirect AHCI Data Register
Register (D31:F2) .............................................................................. 770
AHCI Registers (D31:F2) .................................................................................. 771
23.3.1 AHCI Generic Host Control Registers (D31:F2) ....................................... 771
23.3.2 Port Registers (D31:F2) ...................................................................... 775
24 SMBus Controller Registers (D31:F3) ..................................................................... 789
24.1 PCI Configuration Registers (SMBUS – D31:F3) ................................................... 789
24.1.1 VID – Vendor Identification Register (SMBUS – D31:F3).......................... 789
24.1.2 DID – Device Identification Register (SMBUS – D31:F3) .......................... 789
24.1.3 PCICMD – PCI Command Register (SMBUS – D31:F3) ............................. 790
24.1.4 PCISTS – PCI Status Register (SMBUS – D31:F3) ................................... 790
24.1.5 RID – Revision Identification Register (SMBUS – D31:F3) ........................ 791
24.1.6 PI – Programming Interface Register (SMBUS – D31:F3) ......................... 791
24.1.7 SCC – Sub Class Code Register (SMBUS – D31:F3)................................. 791
24.1.8 BCC – Base Class Code Register (SMBUS – D31:F3) ............................... 791
24.1.10 SVID – Subsystem Vendor Identification Register
(SMBUS – D31:F2/F4) ........................................................................ 792
24.1.11 SID – Subsystem Identification Register
(SMBUS – D31:F2/F4) ........................................................................ 792
24.1.12 INT_LN – Interrupt Line Register (SMBUS – D31:F3) .............................. 792
24.1.13 INT_PN – Interrupt Pin Register (SMBUS – D31:F3)................................ 793
24.1.14 HOSTC – Host Configuration Register (SMBUS – D31:F3) ........................ 793
24.2 SMBus I/O Registers ........................................................................................ 793
24.2.1 HST_STS – Host Status Register (SMBUS – D31:F3) ............................... 794
24.2.2 HST_CNT – Host Control Register (SMBUS – D31:F3) ............................. 795
24.2.3 HST_CMD – Host Command Register (SMBUS – D31:F3)......................... 796
24.2.4 XMIT_SLVA – Transmit Slave Address Register
(SMBUS – D31:F3)............................................................................. 797
24.2.5 HST_D0 – Host Data 0 Register (SMBUS – D31:F3) ................................ 797
24.2.6 HST_D1 – Host Data 1 Register (SMBUS – D31:F3) ................................ 797
24.2.7 Host_BLOCK_DB – Host Block Data Byte Register
(SMBUS – D31:F3)............................................................................. 798
24.2.8 PEC – Packet Error Check (PEC) Register
(SMBUS – D31:F3)............................................................................. 798
24.2.9 RCV_SLVA – Receive Slave Address Register
(SMBUS – D31:F3)............................................................................. 798
24.2.10 SLV_DATA – Receive Slave Data Register (SMBUS – D31:F3)................... 799
24.2.11 AUX_STS – Auxiliary Status Register (SMBUS – D31:F3) ......................... 799
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Intel® 631xESB/632xESB I/O Controller Hub Datasheet
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