NQ6311 データシートの表示（PDF） - Unspecified
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NQ6311 Datasheet PDF : 902 Pages
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21.9.7 TCO1_CNT – TCO1 Control Register...................................................... 726
21.9.8 TCO2_CNT – TCO2 Control Register...................................................... 727
21.9.9 TCO_MESSAGE1 and TCO_MESSAGE2 Registers..................................... 727
21.9.10 TCO_WDCNT – TCO Watchdog Control Register...................................... 727
21.9.11 SW_IRQ_GEN – Software IRQ Generation Register ................................. 728
21.9.12 TCO_TMR – TCO Timer Initial Value Register ......................................... 728
21.10 General Purpose I/O Registers (D31:F0) ............................................................. 728
21.10.1 GPIO Register I/O Address Map ........................................................... 728
21.10.2 GPIO_USE_SEL – GPIO Use Select Register ........................................... 729
21.10.3 GP_IO_SEL – GPIO Input/Output Select Register.................................... 729
21.10.4 GP_LVL – GPIO Level for Input or Output Register .................................. 730
21.10.5 GPO_BLINK – GPO Blink Enable Register ............................................... 731
21.10.6 GPI_INV – GPIO Signal Invert Register ................................................. 731
21.10.7 GPIO_USE_SEL2 – GPIO Use Select 2 Register[63:32] ............................ 732
21.10.8 GP_IO_SEL2 – GPIO Input/Output Select 2 Register[63:32] .................... 733
21.10.9 GP_LVL2 – GPIO Level for Input or Output 2 Register[63:32]................... 733
22 IDE Controller Registers (D31:F1).......................................................................... 735
22.1 PCI Configuration Registers (IDE – D31:F1) ........................................................ 735
22.1.1 VID – Vendor Identification Register (IDE – D31:F1)............................... 736
22.1.2 DID – Device Identification Register (IDE – D31:F1) ............................... 736
22.1.3 PCICMD – PCI Command Register (IDE – D31:F1) .................................. 736
22.1.4 PCISTS – PCI Status Register (IDE – D31:F1) ........................................ 737
22.1.5 RID – Revision Identification Register (IDE – D31:F1) ............................. 737
22.1.6 PI – Programming Interface Register (IDE – D31:F1) .............................. 737
22.1.7 SCC – Sub Class Code Register (IDE – D31:F1)...................................... 738
22.1.8 BCC – Base Class Code Register (IDE – D31:F1) .................................... 738
22.1.9 CLS – Cache Line Size Register (IDE – D31:F1)...................................... 738
22.1.10 PMLT – Primary Master Latency Timer Register
(IDE – D31:F1).................................................................................. 738
22.1.11 PCMD_BAR – Primary Command Block Base Address
Register (IDE – D31:F1) ..................................................................... 739
22.1.12 PCNL_BAR – Primary Control Block Base Address
Register (IDE – D31:F1) ..................................................................... 739
22.1.13 SCMD_BAR – Secondary Command Block Base Address
Register (IDE D31:F1) ........................................................................ 739
22.1.14 SCNL_BAR – Secondary Control Block Base Address
Register (IDE D31:F1) ........................................................................ 739
22.1.15 BM_BASE – Bus Master Base Address Register
(IDE – D31:F1).................................................................................. 740
22.1.16 IDE_SVID – Subsystem Vendor Identification
(IDE – D31:F1).................................................................................. 740
22.1.17 IDE_SID – Subsystem Identification Register
(IDE – D31:F1).................................................................................. 740
22.1.18 INTR_LN – Interrupt Line Register (IDE – D31:F1) ................................. 741
22.1.19 INTR_PN – Interrupt Pin Register (IDE – D31:F1) ................................... 741
22.1.20 IDE_TIMP – IDE Primary Timing Register (IDE – D31:F1) ........................ 741
22.1.21 IDE_TIMS – IDE Secondary Timing Register
(IDE – D31:F1).................................................................................. 742
22.1.22 SLV_IDETIM – Slave (Drive 1) IDE Timing Register
(IDE – D31:F1).................................................................................. 743
22.1.23 SDMA_CNT – Synchronous DMA Control Register
(IDE – D31:F1).................................................................................. 743
22.1.24 SDMA_TIM – Synchronous DMA Timing Register
(IDE – D31:F1).................................................................................. 743
22.1.25 IDE_CONFIG – IDE I/O Configuration Register
(IDE – D31:F1).................................................................................. 744
22.1.26 ATC – APM Trapping Control Register (IDE – D31:F1) ............................. 745
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Intel® 631xESB/632xESB I/O Controller Hub Datasheet
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