V54C3128404V データシートの表示（PDF） - Mosel Vitelic Corporation

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V54C3128404V

128Mbit SDRAM 3.3 VOLT, BGA PACKAGE 8M X 16 16M X 8 32M X 4

Mosel Vitelic Corporation  

MOSEL VITELIC

Block Diagram

V54C3128(16/80/40)4V(BGA)

x8 Configuration

Column Addresses

A0 - A9, AP, BA0, BA1

Row Addresses

A0 - A11, BA0, BA1

Column address

counter

Column address

buffer

Row address

buffer

Refresh Counter

Row decoder

Memory array

Bank 0

4096 x 1024

x 8 bit

Row decoder

Memory array

Bank 1

4096 x 1024

x 8 bit

Row decoder

Memory array

Bank 2

4096 x 1024

x 8 bit

Row decoder

Memory array

Bank 3

4096 x 1024

x 8 bit

Input buffer Output buffer

I/O1-I/O8

Control logic & timing generator

V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001

4

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