V54C3128404V データシートの表示（PDF） - Mosel Vitelic Corporation

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V54C3128404V

128Mbit SDRAM 3.3 VOLT, BGA PACKAGE 8M X 16 16M X 8 32M X 4

Mosel Vitelic Corporation  

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

128Mbit SDRAM

3.3 VOLT, BGA PACKAGE

8M X 16

16M X 8

32M X 4

System Frequency (fCK)

Clock Cycle Time (tCK3)

Clock Access Time (tAC3) CAS Latency = 3

Clock Access Time (tAC2) CAS Latency = 2

6

166 MHz

6 ns

5.4 ns

5.4 ns

7PC

143 MHz

7 ns

5.4 ns

5.4 ns

PRELIMINARY

7

143 MHz

7 ns

5.4 ns

6 ns

8PC

125 MHz

8 ns

6 ns

6 ns

Features

s 4 banks x 2Mbit x 16 organization

s 4 banks x 4Mbit x 8 organization

s 4 banks x 8Mbit x 4 organization

s High speed data transfer rates up to 166 MHz

s Full Synchronous Dynamic RAM, with all signals

referenced to clock rising edge

s Single Pulsed RAS Interface

s Data Mask for Read/Write Control

s Four Banks controlled by BA0 & BA1

s Programmable CAS Latency: 2, 3

s Programmable Wrap Sequence: Sequential or

Interleave

s Programmable Burst Length:

1, 2, 4, 8 for Sequential Type

1, 2, 4, 8 for Interleave Type

s Multiple Burst Read with Single Write Operation

s Automatic and Controlled Precharge Command

s Random Column Address every CLK (1-N Rule)

s Power Down Mode

s Auto Refresh and Self Refresh

s Refresh Interval: 4096 cycles/64 ms

s Available in 60 Pin WBGA

s LVTTL Interface

s Single +3.3 V ±0.3 V Power Supply

Description

The V54C3128(16/80/40)4V(BGA) is a four bank

Synchronous DRAM organized as 4 banks x 2Mbit

x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.

The V54C3128(16/80/40)4V(BGA) achieves high

speed data transfer rates up to 166 MHz by employ-

ing a chip architecture that prefetches multiple bits

and then synchronizes the output data to a system

clock

All of the control, address, data input and output

circuits are synchronized with the positive edge of

an externally supplied clock.

Operating the four memory banks in an inter-

leaved fashion allows random access operation to

occur at higher rate than is possible with standard

DRAMs. A sequential and gapless data rate of up to

166 MHz is possible depending on burst length,

CAS latency and speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

0°C to 70°C

Package Outline

B

6

•

•

Access Time (ns)

7PC

7

•

•

8PC

•

Power

Std.

L

•

•

Temperature

Mark

Blank

V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001

1

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