QL80FC-PQ208I データシートの表示（PDF） - QuickLogic Corporation
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QL80FC-PQ208I Datasheet PDF : 21 Pages
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QL80FC - QuickFCTM
Async_rst
TxOut[19:0]
TxClk125_in
RxIn[19:0]
RxClk125_in
RxComDet
ResIn[2:0]
TenbMode
Clk_rst
TxRst
TxData[31:0]
TxRData[39:32]
TxCrcEn
TxIFIdleEn
TxRawEn
TxKChar
TxClk125
TxClk63
RxData[31:0]
RxRData[39:32]
RxRawEn
RxKChar
RxSgpBus[14:0]
RxCrcRdy
RxCrcOK
RxCrcEn
RxIFIdleEn
RxLOSync
RxLOSIdx[3:0]
RxInvChar
RxClk125
RxClk63
RxRst
ResOut[2:0]
8
SIGNAL DEFINITIONS
input
output
input
input
input
input
input
Dedicated I/O Pins
active high, asynchronous reset
data transmitted to SERDES (only lines [9:0] are used in 10 bit mode)
transmit clock up to 125 MHz
data received from SERDES
receive clock up to 125 MHz
Fibre Channel comma character detected
reserved for QuickLogic use, hold low or high
Customizable Interface Signals
input
Input
output
input
input
input
Input
input
input
output
output
output
output
input
output
output
output
output
input
input
output
output
output
output
output
output
output
enables 10 bit interface to SERDES when asserted
Stops TxClk63 and RxClk63 when high. Tie Low.
active high reset signal for transmit path, synchronous with TxClk63
32 bit Fibre Channel word to be encoded for transmit path
only used when TxRawEn is asserted. Combines with TxData to
construct 40 bit raw data for transmit path
enables CRC error value generation when asserted
enables Intra-Frame IDLE support for transmit path when asserted
select between raw and encoded data modes for transmit data path
indicates that the most significant byte of data word is a K character
full speed transmit clock up to 125 MHz (use the rising edge)
half speed transmit clock up to 63 MHz (use the rising edge)
32 bit Fibre Channel word decoded by the ENDEC receive path.
only used when RxRawEn is asserted. Combines with RxData to
construct 40 bit raw data through the ENDEC receive path
select between raw and encoded data modes for receive data path
asserted when most significant byte of data word is a K character
bus indicating when an ordered set is detected. One signal line is asserted
corresponding to the type of ordered set detected:
[0] – SOF
[5] – NOS
[10] – CLS
[1] – EOF
[6] – LR
[11] – MRK
[2] – IDLE
[7] – LRR
[12] – LIP
[3] – R_RDY
[8] – ARB
[13] – LPE
[4] – OLS
[9] – OPN
[14] – LPB
asserted when available data is a CRC word
asserted when CRC remainder is zero
enables CRC error checking for the receive data path when asserted
enables Intra-Frame IDLE support for receive path when asserted
asserted when bit synchronization with the SERDES has been lost
index indicating state of Loss of Sync state machine
asserted when available data has an invalid encoding error
full speed receive clock up to 125 MHz (use the rising edge)
half speed receive clock up to 63 MHz (use the rising edge)
active high reset signal for receive data path, synchronous with RxClk63
reserved for QuickLogic use, do not connect to these outputs
8Preliminary
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