QL80FC-PQ208I データシートの表示（PDF） - QuickLogic Corporation

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QL80FC-PQ208I

QuickLogic QL80FC Programmable Fibre Channel ENDEC

QuickLogic Corporation 

QL80FC - QuickFCTM

acters from the SERDES receiver (one 10-bit charac-

ter in 10-bit mode), decodes them, and outputs a 4-

byte user data word.

The QL80FC has a system interface that emulates a

synchronous FIFO for ease of use. FIFOs allow maxi-

mum sustained performance of 400 MB/s running a

full duplex link. Their function is to handle the asyn-

chronous interface between the bus data rate and the

different serial data rates, and handle phase and fre-

quency differences inherent in serial links. Internal

FIFOs of 352 x 36 or external FIFOs can be used to

expand the buffering to accommodate multiple

frames.

The QL80FC includes the hardware necessary for

packetized data protection. Framing functions are

provided via Fibre Channel compliant command

words (ordered sets) for Start of Frame and End of

Frame. CRC generation and data frame verification

protect the Fibre Channel frame header and data

field when these framing functions are used.

The device provides a microprocessor interface that

allows the user to manage the serial link. Signals are

also provided to decode serial link error conditions

and differentiate between data and commands. The

QL80FC implements link synchronization with the

SERDES chip through the Loss of Synchronization

State Machine (LOS) as required by the ANSI FC-PH

specification. The LOS manages receiver word syn-

chronization with the RxComDet (comma detect) sig-

nal.

The QL80FC is a versatile part that allows the system

designer to create proprietary or Fibre Channel com-

pliant serial links by taking advantage of some, or all,

of the Fiber Channel compliant features. It has a

number of useful features for system designers of

proprietary links. One such feature is the ability to

send intraframe IDLEs. These characters are auto-

matically sent if the FIFO is empty, but they do not

affect the CRC. In this mode the QL80FC allows

simple interfacing to systems where the flow of data

may be interrupted.

EMBEDDED DESIGN

FUNCTIONAL DESCRIPTION

Embedded Design Functional Description

The embedded FC-1 and FC-2 layers are divided into

two functional groupings: the Transmit data path and

the Receive data path. A functional diagram for the

Transmit path is included in Figure 2.

User Programmable

Logic

Clk_rst

TxClk125_out

TxClk63

TxRData[39:32]

Embedded Fibre Channel ENDEC

Clk_rst To receive data path

/2

TxClk125_in

TxData[31:0]

TxIFIdleEn

TxCrcEn

TxKChar

TxRawEn

TenbMode

TxRst

CRC Generation

8b/10b Encoder

TxOut[19:0]

(only [9:0] used

in 10b mode)

TxClk63 Sync

Reset Circuit

Async_rst

Async_rst

To receive data path TenbMode

FIGURE 2. Customizable ENDEC Chip Functional Block Diagram - Transmit and LCSM Data Paths

3

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