QL80FC-PQ208I データシートの表示（PDF） - QuickLogic Corporation

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QL80FC-PQ208I

QuickLogic QL80FC Programmable Fibre Channel ENDEC

QuickLogic Corporation 

QL80FC - QuickFCTM

QuickLogic QL80FC Programmable Fibre Channel ENDEC

QL80FC - QuickFC

FEATURES

Features

I ANSI Fibre Channel (FC) compatibility

I Data rates up to 2.5 Gb/s supported

I 2.5Gb/s Simplex (200 MByte/s) or Duplex

(400 MByte/s) Mode

I Compatible with standard SERDES components

I 32 bit synchronous FIFO system interface

I Tx and Rx internal FIFO for system applications

without external FIFOs

I Selectable 20-bit/10-bit encoded transmission

character interface to SERDES

I 8b/10b Encoding/Decoding

I CRC Calculation and checking per FC standard

I Fibre Channel Loss of Synchronization (LOS) state

machine

I Support for arbitrated loops

I IntraFrame idles support for proprietary links

I “Raw” data path for the injection of encoding and

CRC errors into the bitsteam for use in testing link

error handling functions

I 3.3V operating voltage

I 3.3V CMOS I/O, 5.0V CMOS tolerant inputs

I 208 PQFP and 456 PBGA packages available

EXTENDED FEATURES

Extended Features

Extended features that can be designed into the user

customizable logic:

I Fibre Channel Link Control State Machine (LCSM)

I RRDY credit management for link flow control

I Microprocessor interface to configure various link

modes

I BIST functions support link bit error rate

measurements

DUAL PORT SRAM

Dual Port SRAM

I 22 blocks (total of 25,344 bits) of dual-port RAM

I Configurable as RAM, ROM or FIFO

I Can be configured as two internal FIFOs of up to

352 x 36 in size

I Configurable RAM array sizes (by 2, 4, 9, 18)

I <5ns access times, 160+Mhz FIFOs

HIGH SPEED CUSTOMIZABLE LOGIC

High Speed Customizable Logic

I Up to 269 customizable I/O pins

I 751 Logic cells

I 300 MHz 16-bit counters, 400 MHz Data paths

I Mux-Based architecture; non-volatile technology

I Completely customizable for any digital application

10 bit/20 bit

10 bit/20 bit

Transmit

Receive

Fibre Channel ENDEC

Customizable

Logic Cells

RAM Blocks

22 Blocks (25K bits)

IO Pins

Fibre Channel Block Diagram

1

Rev A

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