DESCRIPTION
STP3052D is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology.
This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application. Such as DC/DC converter and Desktop computer power management.
The package is universally preferred for commercial industrial surface mount applications.

FEATURE
• -30V/-25.0A, RDS(ON) = 45mΩ (Typ.)
   @VGS = -10V
• -30V/-16.0A, RDS(ON) = 78mΩ
   @VGS =-5.0V
• Super high density cell design for
   extremely low RDS(ON)
• Exceptional on-resistance and
   maximum DC current capability
• TO-252,TO-251 package design