GENERAL DESCRIPTION
The QL80FC device in the QuickLogic QuickFC ESP (Embedded Standard Product) family provides a completely integrated configurable Fibre Channel Encoder/Decoder interface solution combined with customizable logic. This device provides a means to receive and transmit high-speed serial data and implement a Fibre Channel Link interface or any proprietary high-speed serial link.

FEATURES
■ ANSI Fibre Channel (FC) compatibility
■ Data rates up to 2.5 Gb/s supported
■ 2.5Gb/s Simplex (200 MByte/s) or Duplex (400 MByte/s) Mode
■ Compatible with standard SERDES components
■ 32 bit synchronous FIFO system interface
■ Tx and Rx internal FIFO for system applications without external FIFOs
■ Selectable 20-bit/10-bit encoded transmission character interface to SERDES
■ 8b/10b Encoding/Decoding
■ CRC Calculation and checking per FC standard
■ Fibre Channel Loss of Synchronization (LOS) state machine
■ Support for arbitrated loops
■ IntraFrame idles support for proprietary links
■ “Raw” data path for the injection of encoding and CRC errors into the bitsteam for use in testing link error handling functions
■ 3.3V operating voltage
■ 3.3V CMOS I/O, 5.0V CMOS tolerant inputs
■ 208 PQFP and 456 PBGA packages available

EXTENDED FEATURES
Extended features that can be designed into the user customizable logic:
■ Fibre Channel Link Control State Machine (LCSM)
■ RRDY credit management for link flow control
■ Microprocessor interface to configure various link modes
■ BIST functions support link bit error rate measurements

DUAL PORT SRAM
■ 22 blocks (total of 25,344 bits) of dual-port RAM
■ Configurable as RAM, ROM or FIFO
■ Can be configured as two internal FIFOs of up to 352 x 36 in size
■ Configurable RAM array sizes (by 2, 4, 9, 18)
■ <5ns access times, 160+Mhz FIFOs

HIGH SPEED CUSTOMIZABLE LOGIC
■ Up to 269 customizable I/O pins
■ 751 Logic cells
■ 300 MHz 16-bit counters, 400 MHz Data paths
■ Mux-Based architecture; non-volatile technology
■ Completely customizable for any digital application