QL80FC-PB456C データシートの表示（PDF） - QuickLogic Corporation
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QL80FC-PB456C Datasheet PDF : 21 Pages
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QL80FC - QuickFCTM
The Write Enable (WE) line acts as a clock enable for
synchronous write operation. The Read Enable (RE)
acts as a clock enable for synchronous READ opera-
tion (ASYNCRD input low), or as a flow-through
enable for asynchronous READ operation (ASYN-
CRD input high).
RAM Module
MODE[1:0]
W A[a:0]
W D[w:0]
ASYNCRD
RA[a:0]
RD[w:0]
WE
W CLK
RE
RCLK
FIGURE 5. RAM Module
Designers can cascade multiple RAM modules to
increase the depth or width allowed in single modules
by connecting corresponding address lines together
and dividing the words between modules. This
approach allows up to 512-deep configurations as
large as 16 bits wide in the QL80FC device.
A similar technique can be used to create depths
greater than 512 words. In this case, address signals
higher than the eighth bit are encoded onto the write
enable (WE) input for WRITE operations. The READ
data outputs are multiplexed together using encoded
higher READ address bits for the multiplexer
SELECT signals.
JTAG Support
JTAG SUPPORT
JTAG pins support IEEE standard 1149.1a to pro-
vide boundary scan capability for the QL80FC
device. Six pins are dedicated to JTAG and program-
ming functions on each QL80FC device, and are
unavailable for general design input and output sig-
nals. TDI, TDO, TCK, TMS, and TRSTB are JTAG
pins. A sixth pin, STM, is used only for program-
ming.
DEVELOPMENT TOOLS
Software support for the QL80FC device is available
through the QuickWorksTM development package.
This turnkey PC-based QuickWorks package, shown
in Figure 6, provides a complete ESP software solu-
tion with design entry, logic synthesis, place and
route, and simulation. QuickWorks includes VHDL,
Verilog, schematic, and mixed-mode entry with fast
and efficient logic synthesis provided by the inte-
grated Synplicity Synplify LiteTM tool, specially tuned
to take advantage of the QL80FC architecture.
QuickWorks also provides functional and timing sim-
ulation for guaranteed timing and source-level debug-
ging.
The UNIX-based QuickToolsTM package is a subset of
QuickWorks and provides a solution for designers
who use schematic-only design flow or third-party
tools for design entry, synthesis, or simulation.
Third Party
Design
Entry
& Synthesis
QuickWorksDesign Software
SCS
Tools
VHDL/
Schematic Verilog
Mixed-Mode Design
Turbo
HDL Editor
Third Party
Simulation
SpDE
Synplify-
HDL
Synthesis
Simulator
Silos III Aldec
FIGURE 6. QuickWorks Tool Suite
Development Tools
10
10Preliminary
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