DESCRIPTION
The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. PMC-Sierra also offers a software device control package for the AAL1gator-32 device.

FEATURES
The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. PMC-Sierra also offers a software device control package for the AAL1gator-32 device.
• Compliant with the ATM Forum’s Circuit Emulation Services (CES) specification (AF-VTOA-0078), and the ITU-T I.363.1
• Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with the ATM Forum’s DBCES specification (AF-VTOA-0085). Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis.
• Supports non-DBCES idle channel detection by activating a queue when any of its constituent time slots are active, and deactivating a queue when all of its constituent time slots are inactive.
• Provides AAL1 segmentation and reassembly of 16 individual E1 or T1 lines, 8 H-MVIP lines at 8 MHz, or 2 E3 or DS3 or STS-1 unstructured lines.
• Using the optional Scalable Bandwidth Interconnect (SBI) Interface, provides AAL1 segmentation and reassembly of up to 32 T1, E1, or 2 DS3 links. In SBI mode can map any SBI tributary to any of the 32 AAL1 links. Supports floating and locked tributaries as well as unframed, framed without CAS and framed with CAS tributaries. CAS is only supported on Synchronous tributaries.
• Provides a standard UTOPIA level 2 Interface which optionally supports parity and runs up to 52 MHz. Only Cell Level Handshaking is supported. In MPHY mode, can act like a single port or 4 port device. The following modes are supported:
   • 8/16-bit Level 2, Multi-Phy Mode (MPHY)
   • 8/16-bit Level 1, SPHY
   • 8-bit Level 1, ATM Master
• Provides an optional 8/16-bit Any-PHY slave interface.
• Supports up to 1024 Virtual Channels (VC).
• Supports n x 64 (consecutive channels) and m x 64 (non-consecutive channels) structured data format.
• Provides transparent transmission of Common Channel Signaling (CCS) and Channel Associated Signaling (CAS). Provides for termination of CAS signaling.
• Allows the CAS nibble to be coincident with either the first or second nibble of the data.
• Provides per-VC data and signaling conditioning in the transmit cell direction and per DS0 data and signaling conditioning in the transmit line direction. Data and signaling conditioning can be individually enabled. Includes DS3 AIS conditioning support in both directions. Transmit line conditioning options include programmable byte pattern, pseudo-random pattern or old data. Conditioning automatically occurs on underruns.
• In Cell Transmit direction, provides per-VC configuration of time slots allocated, CAS signaling support, partial cell size, data and signaling conditioning, ATM Cell header definition. Generates AAL1 sequence numbers, pointers and SRTS values in accordance with ITU-T I.363.1. Multicast connections are supported.
• In Cell Transmit direction provides counters for:
   • Conditioned cells transmitted for each queue
   • Cells which were suppressed for each queue
   • Total number of cells transmitted for each queue
• In Cell Receive direction, provides per-VC configuration of time slots allocated, CAS signaling support, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. Processes AAL1 headers in accordance with ITU-T I.363.1.
• In Cell Receive direction, supports the Fast Sequence Number processing algorithm on all types of connections and Robust Sequence Number processing on Unstructured Data Format (UDF) connections. Cells are inserted/dropped to maintain bit integrity on lost or misinserted cells. Bit integrity is maintained through any single errored cell or up to six lost cells. Bit integrity can also optionally be maintained even if an underrun occurs. Pointer bytes, signaling bytes, and bitmask bytes are taken into account. Cell insertion options include a programmable single byte pattern, pseudo-random data, or old data .
• In Cell Receive direction provides counters for the following events which include all counters required by the ATM Forum’s CES-IS 2.0 MIB:
   • Incorrect sequence numbers per queue
   • Incorrect sequence number protection fields per queue
   • Total number of received cells per queue
   • Total number of dropped cells per queue
   • Total number of underruns per queue
   • Total number of lost cells per queue
   • Total number of overruns per queue
   • Total number of reframes per queue
   • Total number of pointer parity errors per queue
   • Total number of misinserted cells per queue
   • Total number of OAM or non-data cells received
   • Total number of OAM or non-data cells dropped.
• For each receive queue the following sticky bits are maintained:
   • Cell received
   • Structured pointer rule error detected
   • DBCES bitmask parity error
   • Cell dropped due to blank allocation table
   • Cells dropped due to pointer search
   • Cell dropped due to forced underrun
   • Cell dropped due to sequence number processing algorithm
   • Valid pointer was received
   • Pointer parity error detected
   • SRTS resume from an underrun condition
   • SRTS underrun occurred
   • Resume occurred from an underrun condition
   • Pointer reframe occurred
   • Overrun condition detected
   • Cell received while in an underrun

APPLICATIONS
• Multi-service ATM Switch
• ATM Access Concentrator
• Digital Cross Connect
• Computer Telephony Chassis with ATM infrastructure
• Wireless Local Loop Back Haul
• ATM Passive Optical Network Equipment