OVERVIEW
ISSI's 128Mb Synchronous DRAM  achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDARM is organized as follows.

FEATURES
• Clock frequency: 133 100, MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Power supply VDD VDDQ
  IS42LS81600A 2.5V 1.8V (2.5V tolerant)
  IS42LS16800A 2.5V 1.8V (2.5V tolerant)
  IS42LS32400A 2.5V 1.8V (2.5V tolerant)
  IS42S81600A 3.3V 3.3V
  IS42S16800A 3.3V 3.3V
  IS42S32400A 3.3V 3.3V
• LVTTL interface
• Programmable burst length – (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Extended Mode Register
• Programmable Power Reduction Feature by partial array activation during Self-Refresh
• Auto Refresh (CBR)
• Temp. Compensated Self Refresh.
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CASlatency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Industrial Temperature Availability