DEVICE OVERVIEW
ISSI’s 128-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 134,217,728-bit memory array is internally organized as four banks of 32M-bit to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. 

FEATURES
• Clock Frequency: 200, 166, 100 MHz
• Power supply (VDD and VDDQ): 2.5V
• SSTL 2 interface
• Four internal banks to hide row Pre-charge
   and Active operations
• Commands and addresses register on positive
   clock edges (CLK)
• Bi-directional Data Strobe signal for data capture
• Differential clock inputs (CLK and CLK) for
   two data accesses per clock cycle
• Data Mask feature for Writes supported
• DLL aligns data I/O and Data Strobe transitions
   with clock inputs
• Half-strength and Matched drive strength
   options
• Programmable burst length for Read and Write
   operations
• Programmable CAS Latency (3, 4, 5 clocks)
• Programmable burst sequence: sequential or
   interleaved
• Burst concatenation and truncation supported
   for maximum data throughput
• Auto Pre-charge option for each Read or Write
   burst
• 4096 refresh cycles every 32ms
• Auto Refresh and Self Refresh Modes
• Pre-charge Power Down and Active Power
   Down Modes
• Industrial Temperature Availability
• Lead-free Availability