datasheetbank_Logo
データシート検索エンジンとフリーデータシート
HOME  >>>  Integral Corp.  >>> IN74ACT109D PDF

IN74ACT109D データシート - Integral Corp.

IN74ACT109 image

部品番号
IN74ACT109D

コンポーネント説明

Other PDF
  no available.

PDF
DOWNLOAD     

page
5 Pages

File Size
180 kB

メーカー
INTE-ElectronicGRAL
Integral Corp. INTE-ElectronicGRAL

DUAL J-K FLIP-FLOP WITH SET AND RESET
High-Speed Silicon-Gate CMOS

The IN74ACT109 is identical in pinout to the LS/ALS109, HC/HCT109. The IN74ACT109 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of two J-K flip-flops with individual set, reset, and clock inputs. Changes at the inputs are reflected at the outputs with the next low-to-high transition of the clock. Both Q to Q outputs are available from each flip-flop.

• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• Outputs Source/Sink 24 mA

Page Link's: 1  2  3  4  5 

部品番号
コンポーネント説明
PDF
メーカー
Dual “J-K” Flip-Flop with Set and Reset
Intersil
Dual J-K Flip-Flop with Set and Reset
Motorola => Freescale
Dual J-K Flip-Flop with Set and Reset
IK Semicon Co., Ltd
Dual J-K Flip-Flop with Set and Reset
ON Semiconductor
Dual “J-K” Flip-Flop with Set and Reset
Intersil
Dual J-K Flip-Flop with set and Reset
Kodenshi Auk Co., LTD
Dual J-K Flip-Flop with Set and Reset
Kodenshi Auk Co., LTD
Dual J-K Flip-Flop with Set and Reset
Kodenshi Auk Co., LTD
Dual J-K Flip-Flop with Set and Reset
System Logic Semiconductor
Dual J-K Flip-Flop with Set and Reset
System Logic Semiconductor

Share Link: GO URL

EnglishEnglish Korean한국어 Japanese日本語 Russianрусский Spanishespañol

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]