Functional description
The AS7C1025 and AS7C31025 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal for high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.

FEATUREs
• AS7C1025 (5V version)
• AS7C31025 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
    - 12/15/20 ns address access time
    - 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
    - 715 mW (AS7C1025) / max @ 12 ns (5V)
    - 360 mW (AS7C31025) / max @ 12 ns (3.3V)
• Low power consumption: STANDBY
    - 27.5 mW (AS7C1025) / max CMOS (5V)
    - 1.8 mW (AS7C31025) / max CMOS (3.3V)
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
    - 32-pin, 300 mil SOJ
    - 32-pin, 400 mil SOJ
    - 32-pin TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA