GENERAL DESCRIPTION
The ADSP-TS101S TigerSHARC processor is an ultra high performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new standard of performance for digital signal processors. The TigerSHARC processor’s static superscalar architecture lets the processor execute up to four instructions each cycle, performing twenty-four 16-bit fixed-point operations or six floating-point operations.

KEY FEATURES
   300 MHz, 3.3 ns Instruction Cycle Rate
   6M Bits of Internal—On-Chip—SRAM Memory
   19 mm x 19 mm (484-Ball) or 27 mm x 27 mm
      (625-Ball) PBGA Package
   Dual Computation Blocks—Each Containing an ALU, a
      Multiplier, a Shifter, and a Register File
   Dual Integer ALUs, Providing Data Addressing and
      Pointer Manipulation
   Integrated I/O Includes 14 Channel DMA Controller,
      External Port, Four Link Ports, SDRAM Controller,
      Programmable Flag Pins, Two Timers, and Timer
      Expired Pin for System Integration
   1149.1 IEEE Compliant JTAG Test Access Port for
      On-Chip Emulation
   On-Chip Arbitration for Glueless Multiprocessing with
      up to Eight TigerSHARC Processors on a Bus

KEY BENEFITS
   Provides High Performance Static Superscalar DSP
      Operations, Optimized for Telecommunications
      Infrastructure and Other Large, Demanding
      Multiprocessor DSP Applications
   Performs Exceptionally Well on DSP Algorithm and I/O
      Benchmarks (See Benchmarks in Table 1 and Table 2)
   Supports Low Overhead DMA Transfers Between
      Internal Memory, External Memory, Memory-Mapped
      Peripherals, Link Ports, Host Processors, and Other
      (Multiprocessor) DSPs
   Eases DSP Programming Through Extremely Flexible
      Instruction Set and High Level Language Friendly DSP
      Architecture
   Enables Scalable Multiprocessing Systems with Low
      Communications Overhead