ADBF539WBBCZ5 データシートの表示（PDF） - Analog Devices
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ADBF539WBBCZ5 Datasheet PDF : 60 Pages
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ADSP-BF539/ADSP-BF539F
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally, an external event or RTC activity wakes up the processor.
When in the sleep mode, assertion of a wake-up event enabled
in the SIC_IWRx register causes the processor to sense the value
of the BYPASS bit in the PLL control register (PLL_CTL). If
BYPASS is disabled, the processor transitions to the full on
mode. If BYPASS is enabled, the processor will transition to the
active mode. When in the sleep mode, system DMA access to L1
memory is not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
such as the RTC may still be running but will not be able to
access internal resources or external memory. This powered-
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous
interrupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the full-on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This sets the internal power
supply voltage (VDDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a nonvolatile
storage device prior to removing power if the processor state is
to be preserved. Since VDDEXT can still be supplied in this mode,
all of the external pins three-state, unless otherwise specified.
This allows other devices that may be connected to the proces-
sor to still have power applied without drawing unwanted
current. The internal supply regulator can be woken up either
by a real-time clock wake-up, by CAN bus traffic, by asserting
the RESET pin, or by an external source via the GPW pin.
Power Savings
As shown in Table 6, the ADSP-BF539/ADSP-BF539F proces-
sors support five different power domains. The use of multiple
power domains maximizes flexibility, while maintaining com-
pliance with industry standards and conventions:
• The 3.3 V VDDRTC power domain supplies the RTC I/O and
logic so that the RTC can remain functional when the rest
of the chip is powered off.
• The 3.3 V MXEVDD power domain supplies the MXVR
crystal and is separate to provide noise isolation.
• The 1.25 V MPIVDD power domain supplies the MXVR
PLL and is separate to provide noise isolation.
• The 1.25 V VDDINT power domain supplies all internal logic
except for the RTC logic and the MXVR PLL.
• The 3.3 V VDDEXT power domain supplies all I/O except for
the RTC and MXVR crystals.
There are no sequencing requirements for the various power
domains.
Table 6. Power Domains
Power Domain
RTC Crystal I/O and Logic
MXVR Crystal I/O
MXVR PLL Analog and Logic
All Internal Logic Except RTC and MXVR PLL
All I/O Except RTC and MXVR Crystals
VDD Range
VDDRTC
MXEVDD
MPIVDD
VDDINT
VDDEXT
The VDDRTC should either be connected to an isolated supply
such as a battery (if the RTC is to operate while the rest of the
chip is powered down) or should be connected to the VDDEXT
plane on the board. The VDDRTC should remain powered when
the processor is in hibernate state and should also remain pow-
ered even if the RTC functionality is not being used in an
application. The MXEVDD should be connected to the VDDEXT
plane on the board at a single location with local bypass capaci-
tors. The MXEVDD should remain powered when the
processor is in hibernate state and should also remain powered
even when the MXVR functionality is not being used in an
application. The MPIVDD should be connected to the VDDINT
plane on the board at a single location through a ferrite bead
with local bypass capacitors.
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive in
that, if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the
ADSP-BF539/ADSP-BF539F processors allow both the proces-
sor input voltage (VDDINT) and clock frequency (fCCLK) to be
dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as
Power Savings Factor
where:
=
-f--C---C--L--K---R--E--D--
fCCLKNOM
V-V----DD--D-D--I-I-NN--T-T--NR--O-E--DM--
2
-t--R---E--D--
tNOM
fCCLKNOM is the nominal core clock frequency.
fCCLKRED is the reduced core clock frequency.
VDDINTNOM is the nominal internal supply voltage.
Rev. F | Page 14 of 60 | October 2013
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