ADBF539WBBCZ5 データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

一致するリスト

ADBF539WBBCZ5

Blackfin Embedded Processor

Analog Devices 

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O mapped UART registers.

The data is double buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. Each UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

Each UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (fSCLK/1,048,576) to

(fSCLK/16) bits per second.

• Supporting data formats from 7 bits to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

Each UART port’s clock rate is calculated as:

UART Clock Rate = 1---6---------U----A--f-SR--C--T-L--K_---D----i--v--i--s-o---r-

where the 16-bit UART_Divisor comes from the UARTx_DLH

register (most significant 8 bits) and UARTx_DLL register (least

significant 8 bits).

In conjunction with the general-purpose timer functions, auto-

baud detection is supported on UART0.

The capabilities of the UARTs are further extended with sup-

port for the Infrared Data Association (IrDA®) Serial Infrared

Physical Layer Link Specification (SIR) protocol.

PROGRAMMABLE I/O PINS

The ADSP-BF539/ADSP-BF539F processor has numerous

peripherals that may not all be required for every application.

Therefore, many of the pins have a secondary function as pro-

grammable I/O pins. There are two types of programmable I/O

pins with slightly different functionality: programmable flags

and general-purpose I/O.

Programmable Flags (GPIO Port F)

There are 16 bidirectional, general-purpose programmable flag

(PF15–0) pins on GPIO Port F. Each programmable flag can be

individually controlled by manipulation of the flag control, sta-

tus, and interrupt registers:

• Flag direction control register – Specifies the direction of

each individual PFx pin as input or output.

• Flag control and status registers – The processors employ a

“write one to modify” mechanism that allows any combi-

nation of individual flags to be modified in a single

instruction, without affecting the level of any other flags.

Four control registers are provided. One register is written

in order to set flag values, one register is written in order to

clear flag values, one register is written in order to toggle

flag values, and one register is written in order to specify a

flag value. Reading the flag status register allows software to

interrogate the sense of the flags.

ADSP-BF539/ADSP-BF539F

• Flag interrupt mask registers – The two flag interrupt mask

registers allow each individual PFx pin to function as an

interrupt to the processor. Similar to the two flag control

registers that are used to set and clear individual flag values,

one flag interrupt mask register sets bits to enable interrupt

function, and the other flag interrupt mask register clears

bits to disable interrupt function. PFx pins defined as

inputs can be configured to generate hardware interrupts,

while output PFx pins can be triggered by software

interrupts.

• Flag interrupt sensitivity registers – The two flag interrupt

sensitivity registers specify whether individual PFx pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

The PFx pins can also be used by the SPI0 and PPI ports as

shown in Table 4, depending on how the peripherals are config-

ured. Care must be taken so that these pins are not used for

multiple purposes simultaneously.

General-Purpose I/O Ports C, D, and E

There are 38 general-purpose I/O pins that are multiplexed with

other peripherals. They are arranged into Ports C, D, and E as

shown in Table 4. The GPIO differ from the programmable

flags on Port F in that the GPIO pins cannot generate interrupts

to the processor.

Table 4. Programmable Flag/GPIO Ports

Peripheral

Alternate Programmable Flag/

GPIO Port Function

PPI

PF15–3

SPORT2

PE7–0

SPORT3

PE15–8

SPI0

PF7–0

SPI1

PD4–0

SPI2

PD9–5

UART1

PD11–10

UART2

CAN

MXVR

PD13–12

PC1–01

PC9–41

1 PC1 and PC4 are open-drain when configured as GPIO outputs.

The general-purpose I/O pins can be individually controlled by

manipulation of the control and status registers. These pins will

not cause interrupts to be generated to the processor but can be

polled to determine their status.

• GPIO direction control register – Specifies the direction of

each individual GPIOx pin as input or output.

• GPIO control and status registers – The processors employ

a “write one to modify” mechanism that allows any combi-

nation of individual GPIO pins to be modified in a single

Rev. F | Page 11 of 60 | October 2013

Share Link: