ADBF539WBBCZ5 データシートの表示（PDF） - Analog Devices
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ADBF539WBBCZ5 Datasheet PDF : 60 Pages
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ADSP-BF539/ADSP-BF539F
PIN DESCRIPTIONS
ADSP-BF539/ADSP-BF539F processor pin definitions are listed
in Table 10.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins. These pins are all
driven high, with the exception of CLKOUT, which toggles at
the system clock rate. If BR is active (whether or not RESET is
asserted), the memory pins are also three-stated. All unused I/O
pins have their input buffers disabled with the exception of the
pins that need pull-ups or pull-downs, as noted in the table.
During hibernate, all outputs are three-stated unless otherwise
noted in Table 10.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
Table 10. Pin Descriptions
Pin Name
Type
Memory Interface
ADDR19–1
O
DATA15–0
I/O
ABE1–0/SDQM1–0
O
BR
I
BG
O
BGH
O
Asynchronous Memory Control
AMS3–0
O
ARDY
I
AOE
O
ARE
O
AWE
O
Flash Control
FCE
I
FRESET
I
Synchronous Memory Control
SRAS
O
SCAS
O
SWE
O
SCKE
O
CLKOUT
O
SA10
O
SMS
O
Timers
TMR0
I/O
TMR1/PPI_FS1
I/O
TMR2/PPI_FS2
I/O
Description
Driver
Type1
Address Bus for Async/Sync Access
A
Data Bus for Async/Sync Access
A
Byte Enables/Data Masks for Async/Sync Access
A
Bus Request (This pin should be pulled high when not used.)
Bus Grant
A
Bus Grant Hang
A
Bank Select
A
Hardware Ready Control (This pin should always be pulled low when not used.)
Output Enable
A
Read Enable
A
Write Enable
A
Flash Enable (This pin is internally connected to GND on the ADSP-BF539.)
Flash Reset (This pin is internally connected to GND on the ADSP-BF539.)
Row Address Strobe
A
Column Address Strobe
A
Write Enable
A
Clock Enable (This pin must be pulled low through a 10 k resistor if hibernate state A
is used and SDRAM contents need to be preserved during hibernate.)
Clock Output
B
A10 Pin
A
Bank Select
A
Timer 0
C
Timer 1/PPI Frame Sync1
C
Timer 2/PPI Frame Sync2
C
Rev. F | Page 21 of 60 | October 2013
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