CY7C68033 データシートの表示（PDF） - Cypress Semiconductor
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CY7C68033 Datasheet PDF : 34 Pages
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CY7C68033, CY7C68034
Table 4. Individual FIFO/GPIF Interrupt Sources
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
INT4VEC Value
0x580
0x584
0x588
0x58C
0x590
0x594
0x598
0x59C
0x5A0
0x5A4
0x5A8
0x5AC
0x5B0
0x5B4
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
EP6EF
EP8EF
EP2FF
EP4FF
EP6FF
EP8FF
GPIFDONE
GPIFWF
Notes
Endpoint 2 Programmable Flag
Endpoint 4 Programmable Flag
Endpoint 6 Programmable Flag
Endpoint 8 Programmable Flag
Endpoint 2 Empty Flag
Endpoint 4 Empty Flag
Endpoint 6 Empty Flag
Endpoint 8 Empty Flag
Endpoint 2 Full Flag
Endpoint 4 Full Flag
Endpoint 6 Full Flag
Endpoint 8 Full Flag
GPIF Operation Complete
GPIF Waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the NX2LP-Flex substitutes its INT4VEC byte.
Therefore, if the high byte (‘page’) of a jump-table address is
preloaded at location 0x554, the automatically inserted
INT4VEC byte at 0x555 directs the jump to the correct address
out of the 14 addresses within the page. When the ISR occurs,
the NX2LP-Flex pushes the program counter onto its stack then
jumps to address 0x553, where it expects to find a ‘jump’
instruction to the ISR Interrupt service routine.
Reset and Wakeup
Reset Pin
The input pin RESET#, resets the NX2LP-Flex when asserted.
This pin has hysteresis and is active LOW. When a crystal is
used as the clock source for the NX2LP-Flex, the reset period
must enable the stabilization of the crystal and the PLL. This
reset period should be approximately 5 ms after VCC has
reached 3.0V. If the crystal input pin is driven by a clock signal,
the internal PLL
3.0V[1]. Figure 5
stabilizes in 200
shows a power-on
μs after VCC has reached
reset condition and a reset
applied during operation. A power-on reset is defined as the time
reset is asserted while power is being applied to the circuit. A
powered reset is defined to be when the NX2LP-Flex has previ-
ously been powered on and operating and the RESET# pin is
asserted.
Cypress provides an application note which describes and
recommends power on reset implementation and can be found
on the Cypress web site. For more information on reset imple-
mentation for the EZ-USB family of products visit the
http://www.cypress.com website.
Figure 5. Reset Timing Plots
RESET#
VCC
TRESET
Power-on Reset
VIL
3.3V
3.0V
0V
RESET#
VCC
VIL
3.3V
0V
TRESET
Powered Reset
Note
1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 μs.
Document #: 001-04247 Rev *F
Page 7 of 34
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