CY7C68033 データシートの表示（PDF） - Cypress Semiconductor
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CY7C68033 Datasheet PDF : 34 Pages
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CY7C68033, CY7C68034
Two Ready IN Signals
The 8051 programs the GPIF unit to test the RDY pins for GPIF
branching. The 56-pin package brings out two signals, RDY[1:0].
Long Transfer Mode
In GPIF Master mode, the 8051 appropriately sets GPIF trans-
action count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 232 transactions.
The GPIF automatically throttles data flow to prevent under- or
over-flow until the full number of requested transactions
complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
ECC Generation[5]
The NX2LP-Flex can calculate ECCs (Error-Correcting Codes)
on data that passes across its GPIF or Slave FIFO interfaces.
There are two ECC configurations:
• Two ECCs, each calculated over 256 bytes (SmartMedia
Standard)
• One ECC calculated over 512 bytes.
The following two ECC configurations are selected by the ECCM
bit. The ECC can correct any one-bit error or detect any two-bit
error.
ECCM = 0
Two 3-byte ECCs, each calculated over a 256-byte block of data.
This configuration conforms to the SmartMedia Standard and is
used by both the NAND boot logic and default NAND firmware
image.
When any value is written to ECCRESET and data is then
passed across the GPIF or Slave FIFO interface, the ECC for the
first 256 bytes of data is calculated and stored in ECC1. The ECC
for the next 256 bytes of data is stored in ECC2. After the second
ECC is calculated, the values in the ECCx registers do not
change until ECCRESET is written again, even if more data is
subsequently passed across the interface.
ECCM = 1
One 3-byte ECC calculated over a 512-byte block of data.
When any value is written to ECCRESET and data is then
passed across the GPIF or Slave FIFO interface, the ECC for the
first 512 bytes of data is calculated and stored in ECC1; ECC2
is unused. After the ECC is calculated, the value in ECC1 does
not change until ECCRESET is written again, even if more data
is subsequently passed across the interface
Autopointer Access
NX2LP-Flex provides two identical autopointers. They are
similar to the internal 8051 data pointers, but with an additional
feature: they can optionally increment after every memory
access. Also, the autopointers can point to any NX2LP-Flex
register or endpoint buffer space.
I2C Controller
NX2LP has one I2C port that the 8051, once running uses to
control external I2C devices. The I2C port operates in master
mode only. The I2C post is disabled at startup and only available
for use after the initial NAND access.
I2C Port Pins
The I2C pins SCL and SDA must have external 2.2-kΩ pull-up
resistors even if no EEPROM is connected to the NX2LP.
I2C Interface General-Purpose Access
The 8051 can control peripherals connected to the I2C bus using
the I2CTL and I2DATA registers. NX2LP provides I2C master
control only and is never an I2C slave.
Note
5. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
Document #: 001-04247 Rev *F
Page 11 of 34
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