DS21448 データシートの表示（PDF） - Maxim Integrated

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DS21448

3.3V E1/T1/J1 Quad Line Interface

Maxim Integrated 

DS21448 3.3V T1/E1/J1 Quad Line Interface

4.3.3 Control Registers

CCR1 (00H): Common Control Register 1

(MSB)

ETS

NRZE

RCLA

ECUE

JAMUX

TTOJ

TTOR

(LSB)

LOTCMC

NAME

ETS

NRZE

RCLA

ECUE

JAMUX

TTOJ

TTOR

LOTCMC

POSITION

CCR1.7

CCR1.6

CCR1.5

CCR1.4

CCR1.3

CCR1.2

CCR1.1

CCR1.0

FUNCTION

E1/T1 Select

0 = E1

1 = T1

NRZ Enable

0 = bipolar data at RPOS/RNEG and TPOS/TNEG

1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive-going pulse when the

device receives a BPV, CV, or EXZ

Receive-Carrier-Loss Alternate Criteria

0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros

1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive zeros

Error Counter Update Enable. A 0-to-1 transition forces the next receive clock cycle to load the

error counter registers with the latest counts and reset the counters. The user must wait a

minimum of two clock cycles (976ns for E1 and 1296ns for T1) before reading the error count

registers to allow for a proper update. See Section 6 for details.

Jitter Attenuator Clock Mux. Controls the source for JACLK (Figure 1-1).

0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK)

1 = JACLK sourced from internal PLL (2.048MHz at MCLK)

TCLK to JACLK. Internally connects TCLK to JACLK (Figure 1-3).

0 = disabled

1 = enabled

TCLK to RCLK. Internally connects TCLK to RCLK (Figure 1-3).

0 = disabled

1 = enabled

Loss-of-Transmit Clock Mux Control. Determines whether the transmit logic should switch to

JACLK if the TCLK input should fail to transition (Figure 1-3).

0 = do not switch to JACLK if TCLK stops

1 = switch to JACLK if TCLK stops

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