ADSST-21065LKCA-264 データシートの表示（PDF） - Analog Devices

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ADSST-21065LKCA-264

High End, Multichannel, 32-Bit Floating-Point Audio Processor

Analog Devices 

8.0

7.0

6.0

5.0

RISE TIME

4.0

3.0

FALL TIME

2.0

1.0

0

0 20 40 60 80 100 120 140 160 180 200

LOAD CAPACITANCE – pF

Figure 8. Typical Rise and Fall Time (0.8 V–2.0 V)

6

5

4

3

2

1

0

–1

–2

0 20 40 60 80 100 120 140 160 180 200

LOAD CAPACITANCE – pF

Figure 9. Typical Output Delay or Hold

SST-Melody-SHARC

Power Dissipation

Total power dissipation has two components: one due to internal

circuitry and one due to the switching of external output drivers.

Internal power dissipation depends on the sequence in which

instructions execute and the data operands involved. See IDDIN

calculation in Electrical Characteristics section. Internal power

dissipation is calculated this way:

PINT = IDDIN ×VDD

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

• Number of output pins that switch during each cycle (O)

• Maximum frequency at which the pins can switch (f)

• Load capacitance of the pins (C)

• Voltage swing of the pins (VDD)

The external component is calculated using:

PEXT = O × C ×VDD2 × f

The load capacitance should include the processor’s package

capacitance (CIN). The frequency f includes driving the load high

and then back low. Address and data pins can drive high and low

at a maximum rate of 1/tCK while in SDRAM burst mode.

Example: Estimate PEXT with the following assumptions:

• A system with one bank of external memory (32-bit)

• Two 1 M ϫ 16 SDRAM chips, each with a control signal

load of 3 pF and a data signal load of 4 pF

• External data writes occur in burst mode, two every 1/tCK

cycles, a potential frequency of 1/tCK cycles/s. Assume 50%

pin switching

• The external SDRAM clock rate is 60 MHz (2/tCK)

REV. 0

–17–

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