ADSST-21065LKCA-264 データシートの表示（PDF） - Analog Devices

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ADSST-21065LKCA-264

High End, Multichannel, 32-Bit Floating-Point Audio Processor

Analog Devices 

SST-Melody-SHARC

OUTPUT DRIVE CURRENT

80

60

3.6V, –40؇C

40

3.3V, +25؇C

VOH

3.1V, +85؇C

20 3.1V, +100؇C

0

–20

3.1V, +100؇C

–40

–60

–80

–100

3.1V, +85؇C

VOL

3.3V, +25؇C 3.6V, –40؇C

–120

0

0.50 1.00 1.50 2.00 2.50 3.00 3.50

SOURCE VOLTAGE – V

Figure 3. Typical Drive Currents

TEST CONDITIONS

Output Disable Time

Output pins are considered to be disabled when they stop driving,

go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

to decay by ∆V is dependent on the capacitive load, CL, and the

load current, IL. This decay time can be approximated by the

following equation:

tDECAY

=

CL × ∆V

IL

The output disable time tDIS is the difference between tMEASURED

and tDECAY as shown in Figure 5. The time tMEASURED is the

interval from when the reference signal switches to when the

output voltage decays ∆V from the measured output high or

output low voltage. tDECAY is calculated with test loads CL and IL,

and with ∆V equal to 0.5 V.

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start driving.

The output enable time tENA is the interval from when a reference

signal reaches a high or low voltage level to when the output has

reached a specified high or low trip point, as shown in Figure 4.

If multiple pins (such as the databus) are enabled, the measure-

ment value is that of the first pin to start driving.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate tDECAY using the previous equation. Choose ∆V to

be the difference between the SST-Melody-SHARC’s output

voltage and the input threshold for the device requiring the hold

time. A typical ∆V will be 0.4 V. CL is the total bus capacitance

(per data line), and IL is the total leakage or three-state current

(per data line). The hold time will be tDECAY plus the minimum

disable time (i.e., tDATRWH for the write cycle).

REFERENCE

SIGNAL

tDIS

VOH (MEASURED)

OUTPUT

VOL (MEASURED)

tMEASURED

tENA

VOH (MEASURED) – ⌬V

VOL (MEASURED) + ⌬V

tDECAY

2.0V

1.0V

VOH (MEASURED)

VOL (MEASURED)

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE

THIS VOLTAGE TO BE

APPROXIMATELY 1.5V.

Figure 4. Output Enable

IOL

TO OUTPUT

PIN

50pF

1.5V

IOH

Figure 5. Equivalent Device Loading for

AC Measurements (Includes All Fixtures)

INPUT OR

OUTPUT

1.5V

1.5V

Figure 6. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

Capacitive Loading

Output delays and holds are based on standard capacitive loads:

50 pF on all pins. The delay and hold specifications given should

be derated by a factor of l.8 ns/50 pF for loads other than the

nominal value of 50 pF. Figure 7 and Figure 8 show how output

rise time varies with capacitance. Figure 9 shows graphically how

output delays and hold vary with load capacitance. (Note that

this graph or derating does not apply to output disable delays; see

the previous section Output Disable time under Test Conditions.)

The graphs of Figures 7, 8, and 9 may not be linear outside the

ranges shown.

18

16

14

12

10

RISE TIME

8

FALL TIME

6

4

2

–16–

0

0 20 40 60 80 100 120 140 160 180 200

LOAD CAPACITANCE – pF

Figure 7. Typical Rise and Fall Time (10%–90% VDD)

REV. 0

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