ADSST-21065LKCA-264 データシートの表示（PDF） - Analog Devices
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ADSST-21065LKCA-264 Datasheet PDF : 20 Pages
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SST-Melody-SHARC
GENERAL DESCRIPTION (continued from page 1)
With 32-bit audio quality, the SST-Melody-SHARC audio
processor auto-detects and decodes audio formats in real-time,
enabling end users to enjoy a theater-quality audio experience in
their homes.
The solutions can be customized to meet the exact requirements
of the application. This audio DSP system allows designers to make
value additions to product features working off the high end base
functionality that they are provided with.
Evaluation boards, sample applications and all necessary software
support (drivers, and so on) are available. The SST-Melody-SHARC
enables OEMs to offer comprehensive and single chip solutions
for advanced features in products for end users. SST-Melody-
SHARC audio processors enable OEMs to produce high quality,
low cost designs featuring decoder algorithms and post processors
for DTS-ES Extended Surround (including both DTS-ES Dis-
creet 6.1 and DTS-ES Matrix 6.1), DTS Neo:6, Dolby Digital,
Dolby Digital EX, Dolby Pro Logic, Dolby Pro Logic II, Dolby
Headphone, DDCE, THX and THX Surround EX, HDCD,
MPEG1 Audio Layer 3 (also known as MP3), MPEG2 Audio,
AAC, MLP, WaveSurround, SRS 3D Sound and Stereo. The
audio processors also include audio encoders for DDCE, MPEG,
and MP3.
The cost of development is reduced with the scalable family of
code-compatible devices enabling common solutions across
product lines. Field upgradeable products with programmable
DSP and an optimized library of routines including Dolby and
DTS suites, multichannel AAC and all others, along with the
best development tools in the industry, reduce the time to market.
SST-Melody-SHARC is the comprehensive answer to the needs
of the high end, high quality digital audio market. It delivers a
realistic high fidelity audio experience along with a maximum num-
ber of features, across price points in the high end DVD markets.
HARDWARE ARCHITECTURE
Hardware architecture covers the interface between DSP and
host microcontroller, command processing, data transfer in
serial and parallel form, data buffer management, algorithm
combinations, MIPS, and memory requirements that are provided.
The multichannel algorithms are implemented and tested on a
demo board “PEGASUS II.” This stand-alone board accepts
compressed digital bit streams as serial input from LD/DVD/CD
players or any stream generator and decodes in real time to
generate a 2-channel or multichannel PCM stream. It has a
microcontroller to scan a small keypad to give commands and
select various options, and an LCD for status display.
The SST-Melody-SHARC family (SST-Melody-SHARC) hard-
ware architecture can be broken up into four blocks:
• The Core Processor
• Dual-Ported SAAM
• External Port
• Input/Output Processor
The hardware architecture of the Melody SHARC is complex.
It has four independent buses for dual data, one for instructions,
and one for I/O fetch. Since the four buses are independent,
multiple transactions take place in a single clock cycle. It has two
external ports, DMA channels, and eight serial ports. It is a
0.35 µm technology IC operating at 3.3 V.
The SST-Melody-SHARC processor can be interfaced to external
peripherals with relative ease. The communication between the
SST-Melody-SHARC processor and a host microcontroller utilizes
the SPI bus. The host microcontroller can be the master and the
SST-Melody-SHARC processor can act as a slave. The peripher-
als can be controlled by the host microcontroller using the SPI
bus. The communication is based on commands and parameters.
Status information regarding the SST-Melody-SHARC decoding is
periodically updated and made available to the host microcontroller.
The block diagram of the SST-Melody-SHARC illustrates the
following architectural features:
• Computation units (ALU, multiplier, and shifter) with a shared
data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• Timers with event capture modes
• On-chip, dual-ported SRAM
• External port for interfacing to off-chip memory and
peripherals
• Host port and SDRAM interface
• DMA controller
• Enhanced serial ports
• JTAG test access port
We will use the Functional Block Diagram as our reference. We
assume the SST-Melody-SHARC communicates with host micro
using either direct DMA access or a dual buffer hardware
mechanism. SST-Melody-SHARC has an on-chip memory
buffer that is used for storing commands/parameters sent by the
host to SST-Melody-SHARC and also status information from
SST-Melody-SHARC to be sent to host micro. SST-Melody-
SHARC has direct access to this memory buffer as it resides
on-chip. Host micro has access to this memory using either
direct DMA access or a dual buffer hardware mechanism.
There is a definite protocol for passing commands and obtaining
status information. Once SST-Melody-SHARC receives a com-
mand from host micro, it will process the same and inform host
micro of the status. These commands initiate actions like encoding
and decoding. Encoding and decoding will result in data process-
ing and the processed data may be delivered over the serial port.
For example, while encoding, the PCM data is accepted through
the serial port from peripherals like an ADC or S/PDIF receiver.
The PCM data is then encoded and stored in an on-chip com-
pressed data buffer. These compressed frames are then
accessible to host micro using a high speed DMA or USB port.
SST-Melody-SHARC, will prepare the compressed frames in the
form of IEC 958 format so that it can be sent out using the serial
port or S/PDIF transmitter. Compressed frames can be down-
loaded by host micro to SST-Melody-SHARC and can be
decoded and the resulting PCM data can be sent on serial port
transmitter. While commands and data are transferred between
host micro and SST-Melody-SHARC over a dual buffer/DMA we
need the help of interrupts and a few general-purpose input/
output lines to provide reliable communication.
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