ML7033 データシートの表示（PDF） - LAPIS Semiconductor Co., Ltd.

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ML7033

Dual-Channel Line Card CODEC

LAPIS Semiconductor Co., Ltd. 

FEDL7033-04

ML7033

BCLK

Shift clock signal input for the PCMIN and the PCMOUT signals. The clock frequency, equal to the data rate, is

256 kHz to 4096 kHz. This signal must be generated from the same clock source as the master clock and

synchronized in phase with the master clock. Please refer to Figures 1 and 2 for more information about the

phase difference between MCK and BCLK.

RSYNC

Receive synchronizing clock input. The PCMIN signals are received in synchronization with this clock. The 8

kHz input clock is generated from the identical clock source as MCK and must be synchronized in phase with

the master clock.

XSYNC

Transmit synchronizing clock input. The PCMOUT signals are transmitted in synchronization with this clock.

The 8 kHz input clock is generated from the identical clock source as MCK and must be synchronized in phase

with the master clock.

PCMIN

Serial PCM data input. The serial PCM data input on the PCMIN pin is converted to analog signals and output

from the AOUTnP pin (or from the AOUTnN pin and the AOUTnP pin) in synchronization with the RSYNC

clock and the BCLK clock.

When in Long Frame Sync Mode (CR0-B4 = “0”), the first bit of the serial PCM data (MSD of channel 1) is

identified at the rising edge of the RSYNC clock.

When in Short Frame Sync Mode (CR0-B4 = “1”), the first bit of the serial PCM data (MSD of channel 1) is

identified at the falling edge of the RSYNC clock.

PCMOUT

Serial PCM data output. Channel 1 data is output in sequential order, from most significant data (MSD) to least

significant data (LSD). Data is synchronized with the rising edge of BCLK.

When in Long Frame Sync Mode (CR0-B4 = “0”), the first bit of PCM data may be output at the rising edge of

the XSYNC signal, depending on the timing between BCLK and XSYNC.

When in Short Frame Sync Mode (CR0-B4 = “1”), the first bit of PCM data may be output at the falling edge of

the XSYNC signal, depending on the timing between BCLK and XSYNC.

This pin is in a high impedance state during power-down. A pull-up resistor must be connected to this pin since

it is an open drain output.

PCMOSY

PCMOSY is asserted to a logic 0 when PCM data is valid on the PCMOUT pin. This includes both normal mode

and power-save mode.

When PCM data is not being output from the PCMOUT pin (including during power-down mode), this pin goes

a logic “1”.

This signal is used to control the TRI-STATE Enable of a backplane line-driver.

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