ML7033 データシートの表示（PDF） - LAPIS Semiconductor Co., Ltd.
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ML7033 Datasheet PDF : 52 Pages
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FEDL7033-04
ML7033
TOUT1, TOUT2
TOUTn is the tone analog output for the corresponding channel. The output signal has an amplitude of 2.5 Vpp
above and below the signal ground voltage (SG). While the device is in power-down mode, or the corresponding
channel is in power-save mode, the related outputs are high impedance.
VDDA, VDDD
+5 V power supply for analog and digital circuits. The VDDA pin is the power pin for the analog circuits. The
VDDD pin is the power pin for the digital circuits. If these signals are connected together externally, The VDDA pin
must be connected to the VDDD pin in the shortest distance on the printed circuit board. Internal to the ML7033,
the VDDA plane is separate from the VDDD plane.
To minimize power supply noise, a 0.1 F bypass capacitor (with excellent high frequency characteristics) and a
10 F electrolytic capacitor should be connected between the VDDA pin and the AG pin. In addition, the same
capacitive network should also be connected between the VDDD pin and the DG pin. If the AG and DG pins are
connected together externally, only one capacitive network is required.
AG, DG
The AG pin is a ground for the analog circuits. The DG pin is a ground for the digital circuits.
The analog ground and the digital ground are separated internally within the device. The AG pin and DG pins
must be connected in the shortest distance on the printed circuit board, and then to system ground with a low
impedance.
SGC
The SGC pin used is to internally generate the signal ground voltage level by connecting a bypass capacitor. The
output impedance is approximately 50 k. Connect a 0.1 F bypass capacitor with excellent high frequency
characteristics between the SGC pin and the AG pin. During power-down mode, the SGC output is at the voltage
level of the AG pin.
SG
The SG pin is the signal ground level output for the system circuits. The output voltage is 2.4 V, the as same as
the SGC pin in a normal operating state. During power-down mode, this output is high impedance.
MCK
Master clock input. Input either 2.048 or 4.096 MHz clock. After turning on the power, the appropriate value
must be written into the MCKSEL bit (CR0-B5) depending upon the desired master clock frequency.
If the supplied master clock frequency and the value of the MCKSEL bit (CR0-B5) do not match, the
power-down control circuit and the MCU interface circuit will continue to operate properly. Access to the
control registers can also occur. However, other circuits may not operate properly.
As for the power-on sequence, please refer to “Power-On Sequence” in the later page.
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