IMSC011 データシートの表示（PDF） - STMicroelectronics

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IMSC011

Link adaptor

STMicroelectronics 

6 Mode 2 parallel interface

6.4.2 Input Status Register

This register contains the data present flag and the interrupt enable control bit for InputInt. The data pres-

ent flag is set to indicate that data in the data input buffer is valid. It is reset low only when the data input

buffer is read, or by Reset. When writing to this register, the data present bit must be written as zero.

The interrupt enable bit can be set and reset by writing to the status register with this bit high or low respec-

tively. When the interrupt enable and data present flags are both high, the InputInt output will be high (sec-

tion 6.5). Resetting interrupt enable will take InputInt low; setting it again before reading the data input

register will set InputInt high again. The interrupt enable bit can be read to determine its status.

When writing to this register, bits 2-7 must be written as zero; this ensures that they will be zero when the

register is read. Failure to write zeroes to these bits may result in undefined data being returned by these

bits during a status register read.

7

6

5

4

3

2

1

0

Interrupt Data

Enable Present

InputInt

&

Figure 6.3 IMS C011 Mode 2 input status register

6.4.3 Output Data Register

Data written to this link adaptor register is transmitted out of the serial link as a data packet. Data should

only be written to this register when the output ready bit in the output status register is high, otherwise data

already being transmitted may be corrupted. Reading this register will result in undefined data being read.

6.4.4 Output Status Register

This register contains the output ready flag and the interrupt enable control bit for OutputInt. The output

ready flag is set to indicate that the data output buffer is empty and a link acknowledge has been received.

It is reset low only when data is written to the data output buffer; it is set high by Reset. When writing to

this register, the output ready bit must be written as zero.

The interrupt enable bit can be set and reset by writing to the status register with this bit high or low respec-

tively. When the interrupt enable and output ready flags are both high, the OutputInt output will be high

(section 6.6). Resetting interrupt enable will take OutputInt low; setting it again whilst the data output reg-

ister is empty will set OutputInt high again. The interrupt enable bit can be read to determine its status.

When writing to this register, bits 2-7 must be written as zero; this ensures that they will be zero when the

register is read. Failure to write zeroes to these bits may result in undefined data being returned by these

bits during a status register read.

6.5 InputInt

The InputInt output is set high to indicate that a data packet has been received from the serial link. It is

inhibited from going high when the interrupt enable bit in the input status register is low (section 6.4.2).

InputInt is reset low when data is read from the input data register (section 6.4.1) and by Reset (page 7).

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