IMSC011 データシートの表示（PDF） - STMicroelectronics

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IMSC011

Link adaptor

STMicroelectronics 

IMS C011

6 Mode 2 parallel interface

The IMS C011 provides an interface between a link and a microprocessor style bus. Operation of the link

adaptor is controlled through the parallel interface bus lines D0-7 by reading and writing various registers

in the link adaptor. Registers are selected by RS0-1 and RnotW, and the chip enabled with notCS.

For convenience of description, the device connected to the parallel side of the link adaptor is presumed

to be a microprocessor, although this will not always be the case.

6.1 D0–7

Data is communicated between a microprocessor bus and the link adaptor via the bidirectional bus lines

D0-7. The bus is high impedance unless the link adaptor chip is selected and the RnotW line is high. The

bus is used by the microprocessor to access status and data registers.

6.2 notCS

The link adaptor chip is selected when notCS is low. Register selectors RS0-1 and RnotW must be valid

before notCS goes low; D0-7 must also be valid if writing to the chip (RnotW low). Data is read by the link

adaptor on the rising edge of notCS.

6.3 RnotW

RnotW, in conjunction with notCS, selects the link adaptor registers for read or write mode. When RnotW

is high, the contents of an addressed register appear on the data bus D0-7; when RnotW is low the data

on D0-7 is written into the addressed register.The state of RnotW is latched into the link adaptor by notCS

going low; it may be changed before notCS returns high, within the timing restrictions given.

6.4 RS0–1

One of four registers is selected by RS0-1. A register is addressed by setting up RS0-1 and then taking

notCS low; the state of RnotW when notCS goes low determines whether the register will be read or writ-

ten. The state of RS0-1 is latched into the link adaptor by notCS going low; it may be changed before

notCS returns high, within the timing restrictions given. The register set comprises a read-only data input

register, a write-only data output register and a read/write status register for each.

RS1 RS0 RnotW Register

0

0

1 Read data

0

0

0 Invalid

0

1

1 Invalid

0

1

0 Write data

1

0

1 Read input status

1

0

0 Write input status

1

1

1 Read output status

1

1

0 Write output status

Table 6.1 IMS C011 Mode 2 register selection

6.4.1 Input Data Register

This register holds the last data packet received from the serial link. It never contains acknowledge pack-

ets. It contains valid data only whilst the data present flag is set in the input status register. It cannot be

assumed to contain valid data after it has been read; a double read may or may not return valid data on

the second read. If data present is valid on a subsequent read it indicates new data is in the buffer. Writing

to this register will have no effect.

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