AD7884AP データシートの表示（PDF） - Analog Devices

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AD7884AP

LC2MOS 16-Bit, High Speed Sampling ADCs

Analog Devices 

The required 3 V reference is derived from the AD780 and

buffered by the high speed amplifier A3 (AD845, AD817, or

equivalent). A4 is a unity gain inverter that provides the –3 V

negative reference. The gain setting resistors are on-chip and are

factory trimmed to ensure precise tracking of VREF+. Figure 6

shows A3 and A4 as AD845s or AD817s. These have the ability to

respond to the rapidly changing reference input impedance.

CIRCUIT DESCRIPTION

Analog Input Section

The analog input section of the AD7884/AD7885 is shown in

Figure 7. It contains both the input signal conditioning and

sample-and-hold amplifier. Note that the analog input is truly

benign. When SW1A goes open circuit to put the SHA into the

hold mode, SW1B is closed. This means that the input resistors,

R1 and R2, are always connected to either virtual ground or

true ground.

R3

3k⍀

3VINF

3VINS

5VINF

5VINS

R1

3k⍀

R2

5k⍀

SW1B

C1

SW1A

AA11

R4

4k⍀

R6

2k⍀

TO 9-BIT

ADC

R5

4k⍀

TO RESIDUE

AMPLIFIER A2

VREF–

AD7884/AD7885

The signal at the output of A2 is proportional to the error

between the first phase result and the actual analog input

signal and is digitized in the second conversion phase. This

second phase begins when the 16-bit DAC and the residue

error amplifier have both settled. First, SW2 is turned off and

SW3 is turned on. Then, the SHA section of the residue

amplifier goes into hold mode. Next SW2 is turned off and

SW3 is turned on. The 9-bit result is transferred to the output

latch and ALU. An error correction algorithm now compensates

for the offset inserted in the residue amplifier section and

errors introduced in the first pass conversion and combines both

results to give the 16-bit answer.

؎3V SIGNAL

FROM INPUT

SHA

R6

2k⍀

R4

4k⍀

0 TO –3V

R5

4k⍀

SW2

VREF–

A2

RESIDUE AMP

+ SHA

SW3

9-BIT

ADC

9

LATCH

+

16

ALU

9

16-BIT

ACCURATE

9

DAC

+3V –3V

R7

2k⍀ R8

2k⍀

Figure 7. AD7884/AD7885 Analog Input Section

When the ± 3VINS and ± 3VINF inputs are tied to 0 V, the

input section has a gain of –0.6 and transforms an input signal of

±5 V to the required ±3 V. When the ± 5VINS and ±5VINF inputs

are grounded, the input section has a gain of –1 and so the analog

input range is now ± 3 V. Resistors R4 and R5, at the amplifier

output, further condition the ± 3 V signal to be 0 V to –3 V. This

is the required input for the 9-bit A/D converter section.

With SW1A closed, the output of A1 follows the input (the

sample-and-hold is in the track mode). On the rising edge of

the CONVST pulse, SW1A goes open circuit and capacitor C1

holds the voltage on the output of A1. The sample-and-hold is

now in the hold mode. The aperture delay time for the sample-

and-hold is nominally 50 ns.

A/D Converter Section

The AD7884/AD7885 uses a two-pass flash technique in order

to achieve the required speed and resolution. When the CONVST

control input goes from low to high, the sample-and-hold ampli-

fier goes into the hold mode and a 0 V to –3 V signal is presented

to the input of the 9-bit ADC. The first phase of conversion

generates the 9 MSBs of the 16-bit result and transfers these to

the latch and ALU combination. They are also fed back to the

9 MSBs of the 16-bit DAC. The 7 LSBs of the DAC are

permanently loaded with 0s. The DAC output is subtracted from

the analog input with the result being amplified and offset in the

Residue Amplifier section.

VREF+F VREF+S VINV VREF–

Figure 8. A/D Converter Section

Timing and Control Section

Figure 9 shows the timing and control sequence for the AD7884/

AD7885. When the part receives a CONVST pulse, the con-

version begins. The input sample-and-hold goes into the hold

mode 50 ns after the rising edge of CONVST and BUSY goes

low. This is the first phase of conversion and takes 3.35 µs to

complete. The second phase of conversion begins when SW2 is

turned off and SW3 is turned on. The residue amplifier and

SHA section (A2 in Figure 8) goes into hold mode at this point

and allows the input sample-and-hold to go back into sample

mode. Thus, while the second phase of conversion is ongoing,

the input sample-and-hold is also acquiring the input signal for

the next conversion. This overlap between conversion and

acquisition allows throughput rates of 166 kSPS to be achieved.

CONVST

BUSY

INPUT

SHA

HOLD

SAMPLE

FIRST PHASE

3.5␮s

SECOND

PHASE

1.8␮s

TACQ

2.5␮s

FIRST PHASE OF CONVERSION

FIRST 9-BIT CONVERSION

DAC SETTLING TIME

RESIDUE AMPLIFIER

SETTLING TIME

SECOND PHASE OF CONVERSION

SECOND 9-BIT CONVERSION

ERROR CORRECTION

OUTPUT LATCH UPDATE

Figure 9. Timing and Control Sequence

REV. E

–9–

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